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< # Allow the bridge to pass through the IO APIC (two pages),
< # everything in the IO address range up to the local APIC, and
< # then the entire PCI address space and beyond
---
> # Allow the bridge to pass through:
> # 1) kernel configured PCI device memory map address: address range
> # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
> # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
> # 3) everything in the IO address range up to the local APIC, and
> # 4) then the entire PCI address space and beyond.
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< AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
< x86_sys.pc.south_bridge.io_apic.pio_addr +
< APIC_range_size - 1),
---
> AddrRange(0xC0000000, 0xFFFF0000),
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< # Reserve the last 16kB of the 32-bit address space for the
< # m5op interface
< X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
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> # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
> # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
> # specific range can pass though bridge to iobus.
> if len(self.mem_ranges) == 1:
> entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
> size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
> range_type=2))
>
> # Reserve the last 16kB of the 32-bit address space for the m5op interface
> entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
>