1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47 image = CowDiskImage(child=RawDiskImage(read_only=True),
48 read_only=False)
49
50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
| 1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47 image = CowDiskImage(child=RawDiskImage(read_only=True),
48 read_only=False)
49
50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
|
58def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None):
| 58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
|
59 IO_address_space_base = 0x80000000000
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
| 59 IO_address_space_base = 0x80000000000
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
|
76 self.physmem = MemClass(range = AddrRange(mdesc.mem()))
77 self.mem_ranges = [self.physmem.range]
| 76 self.mem_ranges = [AddrRange(mdesc.mem())]
|
78 self.bridge.master = self.iobus.slave
79 self.bridge.slave = self.membus.master
| 77 self.bridge.master = self.iobus.slave
78 self.bridge.slave = self.membus.master
|
80 self.physmem.port = self.membus.master
| |
81 self.disk0 = CowIdeDisk(driveID='master')
82 self.disk2 = CowIdeDisk(driveID='master')
83 self.disk0.childImage(mdesc.disk())
84 self.disk2.childImage(disk('linux-bigswap2.img'))
85 self.tsunami = BaseTsunami()
86 self.tsunami.attachIO(self.iobus)
87 self.tsunami.ide.pio = self.iobus.master
88 self.tsunami.ide.config = self.iobus.master
89 self.tsunami.ide.dma = self.iobus.slave
90 self.tsunami.ethernet.pio = self.iobus.master
91 self.tsunami.ethernet.config = self.iobus.master
92 self.tsunami.ethernet.dma = self.iobus.slave
93 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
94 read_only = True))
95 self.intrctrl = IntrControl()
96 self.mem_mode = mem_mode
97 self.terminal = Terminal()
98 self.kernel = binary('vmlinux')
99 self.pal = binary('ts_osfpal')
100 self.console = binary('console')
101 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
102
103 self.system_port = self.membus.slave
104
105 return self
106
| 79 self.disk0 = CowIdeDisk(driveID='master')
80 self.disk2 = CowIdeDisk(driveID='master')
81 self.disk0.childImage(mdesc.disk())
82 self.disk2.childImage(disk('linux-bigswap2.img'))
83 self.tsunami = BaseTsunami()
84 self.tsunami.attachIO(self.iobus)
85 self.tsunami.ide.pio = self.iobus.master
86 self.tsunami.ide.config = self.iobus.master
87 self.tsunami.ide.dma = self.iobus.slave
88 self.tsunami.ethernet.pio = self.iobus.master
89 self.tsunami.ethernet.config = self.iobus.master
90 self.tsunami.ethernet.dma = self.iobus.slave
91 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
92 read_only = True))
93 self.intrctrl = IntrControl()
94 self.mem_mode = mem_mode
95 self.terminal = Terminal()
96 self.kernel = binary('vmlinux')
97 self.pal = binary('ts_osfpal')
98 self.console = binary('console')
99 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
100
101 self.system_port = self.membus.slave
102
103 return self
104
|
107def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None):
| 105def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
|
108 class BaseTsunami(Tsunami):
109 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
110 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
111 pci_func=0, pci_dev=0, pci_bus=0)
| 106 class BaseTsunami(Tsunami):
107 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
108 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
109 pci_func=0, pci_dev=0, pci_bus=0)
|
112
113 physmem = MemClass(range = AddrRange(mdesc.mem()))
114 self = LinuxAlphaSystem(physmem = physmem)
115 self.mem_ranges = [self.physmem.range]
| 110 self = LinuxAlphaSystem()
111 self.mem_ranges = [AddrRange(mdesc.mem())]
|
116 if not mdesc:
117 # generic system
118 mdesc = SysConfig()
119 self.readfile = mdesc.script()
120
121 # Create pio bus to connect all device pio ports to rubymem's pio port
122 self.piobus = NoncoherentBus()
123
| 112 if not mdesc:
113 # generic system
114 mdesc = SysConfig()
115 self.readfile = mdesc.script()
116
117 # Create pio bus to connect all device pio ports to rubymem's pio port
118 self.piobus = NoncoherentBus()
119
|
124 #
125 # Pio functional accesses from devices need direct access to memory
126 # RubyPort currently does support functional accesses. Therefore provide
127 # the piobus a direct connection to physical memory
128 #
129 self.piobus.master = physmem.port
130
| |
131 self.disk0 = CowIdeDisk(driveID='master')
132 self.disk2 = CowIdeDisk(driveID='master')
133 self.disk0.childImage(mdesc.disk())
134 self.disk2.childImage(disk('linux-bigswap2.img'))
135 self.tsunami = BaseTsunami()
136 self.tsunami.attachIO(self.piobus)
137 self.tsunami.ide.pio = self.piobus.master
138 self.tsunami.ide.config = self.piobus.master
139 self.tsunami.ethernet.pio = self.piobus.master
140 self.tsunami.ethernet.config = self.piobus.master
141
142 #
143 # Store the dma devices for later connection to dma ruby ports.
144 # Append an underscore to dma_devices to avoid the SimObjectVector check.
145 #
146 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
147
148 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
149 read_only = True))
150 self.intrctrl = IntrControl()
151 self.mem_mode = mem_mode
152 self.terminal = Terminal()
153 self.kernel = binary('vmlinux')
154 self.pal = binary('ts_osfpal')
155 self.console = binary('console')
156 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
157
158 return self
159
| 120 self.disk0 = CowIdeDisk(driveID='master')
121 self.disk2 = CowIdeDisk(driveID='master')
122 self.disk0.childImage(mdesc.disk())
123 self.disk2.childImage(disk('linux-bigswap2.img'))
124 self.tsunami = BaseTsunami()
125 self.tsunami.attachIO(self.piobus)
126 self.tsunami.ide.pio = self.piobus.master
127 self.tsunami.ide.config = self.piobus.master
128 self.tsunami.ethernet.pio = self.piobus.master
129 self.tsunami.ethernet.config = self.piobus.master
130
131 #
132 # Store the dma devices for later connection to dma ruby ports.
133 # Append an underscore to dma_devices to avoid the SimObjectVector check.
134 #
135 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
136
137 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
138 read_only = True))
139 self.intrctrl = IntrControl()
140 self.mem_mode = mem_mode
141 self.terminal = Terminal()
142 self.kernel = binary('vmlinux')
143 self.pal = binary('ts_osfpal')
144 self.console = binary('console')
145 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
146
147 return self
148
|
160def makeSparcSystem(mem_mode, MemClass, mdesc = None):
| 149def makeSparcSystem(mem_mode, mdesc = None):
|
161 # Constants from iob.cc and uart8250.cc
162 iob_man_addr = 0x9800000000
163 uart_pio_size = 8
164
165 class CowMmDisk(MmDisk):
166 image = CowDiskImage(child=RawDiskImage(read_only=True),
167 read_only=False)
168
169 def childImage(self, ci):
170 self.image.child.image_file = ci
171
172 self = SparcSystem()
173 if not mdesc:
174 # generic system
175 mdesc = SysConfig()
176 self.readfile = mdesc.script()
177 self.iobus = NoncoherentBus()
178 self.membus = MemBus()
179 self.bridge = Bridge(delay='50ns')
180 self.t1000 = T1000()
181 self.t1000.attachOnChipIO(self.membus)
182 self.t1000.attachIO(self.iobus)
| 150 # Constants from iob.cc and uart8250.cc
151 iob_man_addr = 0x9800000000
152 uart_pio_size = 8
153
154 class CowMmDisk(MmDisk):
155 image = CowDiskImage(child=RawDiskImage(read_only=True),
156 read_only=False)
157
158 def childImage(self, ci):
159 self.image.child.image_file = ci
160
161 self = SparcSystem()
162 if not mdesc:
163 # generic system
164 mdesc = SysConfig()
165 self.readfile = mdesc.script()
166 self.iobus = NoncoherentBus()
167 self.membus = MemBus()
168 self.bridge = Bridge(delay='50ns')
169 self.t1000 = T1000()
170 self.t1000.attachOnChipIO(self.membus)
171 self.t1000.attachIO(self.iobus)
|
183 self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'))
184 self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'))
185 self.mem_ranges = [self.physmem.range, self.physmem2.range]
| 172 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
173 AddrRange(Addr('2GB'), size ='256MB')]
|
186 self.bridge.master = self.iobus.slave
187 self.bridge.slave = self.membus.master
| 174 self.bridge.master = self.iobus.slave
175 self.bridge.slave = self.membus.master
|
188 self.physmem.port = self.membus.master
189 self.physmem2.port = self.membus.master
| |
190 self.rom.port = self.membus.master
191 self.nvram.port = self.membus.master
192 self.hypervisor_desc.port = self.membus.master
193 self.partition_desc.port = self.membus.master
194 self.intrctrl = IntrControl()
195 self.disk0 = CowMmDisk()
196 self.disk0.childImage(disk('disk.s10hw2'))
197 self.disk0.pio = self.iobus.master
198
199 # The puart0 and hvuart are placed on the IO bus, so create ranges
200 # for them. The remaining IO range is rather fragmented, so poke
201 # holes for the iob and partition descriptors etc.
202 self.bridge.ranges = \
203 [
204 AddrRange(self.t1000.puart0.pio_addr,
205 self.t1000.puart0.pio_addr + uart_pio_size - 1),
206 AddrRange(self.disk0.pio_addr,
207 self.t1000.fake_jbi.pio_addr +
208 self.t1000.fake_jbi.pio_size - 1),
209 AddrRange(self.t1000.fake_clk.pio_addr,
210 iob_man_addr - 1),
211 AddrRange(self.t1000.fake_l2_1.pio_addr,
212 self.t1000.fake_ssi.pio_addr +
213 self.t1000.fake_ssi.pio_size - 1),
214 AddrRange(self.t1000.hvuart.pio_addr,
215 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
216 ]
217 self.reset_bin = binary('reset_new.bin')
218 self.hypervisor_bin = binary('q_new.bin')
219 self.openboot_bin = binary('openboot_new.bin')
220 self.nvram_bin = binary('nvram1')
221 self.hypervisor_desc_bin = binary('1up-hv.bin')
222 self.partition_desc_bin = binary('1up-md.bin')
223
224 self.system_port = self.membus.slave
225
226 return self
227
| 176 self.rom.port = self.membus.master
177 self.nvram.port = self.membus.master
178 self.hypervisor_desc.port = self.membus.master
179 self.partition_desc.port = self.membus.master
180 self.intrctrl = IntrControl()
181 self.disk0 = CowMmDisk()
182 self.disk0.childImage(disk('disk.s10hw2'))
183 self.disk0.pio = self.iobus.master
184
185 # The puart0 and hvuart are placed on the IO bus, so create ranges
186 # for them. The remaining IO range is rather fragmented, so poke
187 # holes for the iob and partition descriptors etc.
188 self.bridge.ranges = \
189 [
190 AddrRange(self.t1000.puart0.pio_addr,
191 self.t1000.puart0.pio_addr + uart_pio_size - 1),
192 AddrRange(self.disk0.pio_addr,
193 self.t1000.fake_jbi.pio_addr +
194 self.t1000.fake_jbi.pio_size - 1),
195 AddrRange(self.t1000.fake_clk.pio_addr,
196 iob_man_addr - 1),
197 AddrRange(self.t1000.fake_l2_1.pio_addr,
198 self.t1000.fake_ssi.pio_addr +
199 self.t1000.fake_ssi.pio_size - 1),
200 AddrRange(self.t1000.hvuart.pio_addr,
201 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
202 ]
203 self.reset_bin = binary('reset_new.bin')
204 self.hypervisor_bin = binary('q_new.bin')
205 self.openboot_bin = binary('openboot_new.bin')
206 self.nvram_bin = binary('nvram1')
207 self.hypervisor_desc_bin = binary('1up-hv.bin')
208 self.partition_desc_bin = binary('1up-md.bin')
209
210 self.system_port = self.membus.slave
211
212 return self
213
|
228def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
| 214def makeArmSystem(mem_mode, machine_type, mdesc = None,
|
229 dtb_filename = None, bare_metal=False):
230 assert machine_type
231
232 if bare_metal:
233 self = ArmSystem()
234 else:
235 self = LinuxArmSystem()
236
237 if not mdesc:
238 # generic system
239 mdesc = SysConfig()
240
241 self.readfile = mdesc.script()
242 self.iobus = NoncoherentBus()
243 self.membus = MemBus()
244 self.membus.badaddr_responder.warn_access = "warn"
245 self.bridge = Bridge(delay='50ns')
246 self.bridge.master = self.iobus.slave
247 self.bridge.slave = self.membus.master
248
249 self.mem_mode = mem_mode
250
251 if machine_type == "RealView_PBX":
252 self.realview = RealViewPBX()
253 elif machine_type == "RealView_EB":
254 self.realview = RealViewEB()
255 elif machine_type == "VExpress_ELT":
256 self.realview = VExpress_ELT()
257 elif machine_type == "VExpress_EMM":
258 self.realview = VExpress_EMM()
259 self.load_addr_mask = 0xffffffff
260 else:
261 print "Unknown Machine Type"
262 sys.exit(1)
263
264 self.cf0 = CowIdeDisk(driveID='master')
265 self.cf0.childImage(mdesc.disk())
266 # default to an IDE controller rather than a CF one
267 # assuming we've got one
268 try:
269 self.realview.ide.disks = [self.cf0]
270 except:
271 self.realview.cf_ctrl.disks = [self.cf0]
272
273 if bare_metal:
274 # EOT character on UART will end the simulation
275 self.realview.uart.end_on_eot = True
| 215 dtb_filename = None, bare_metal=False):
216 assert machine_type
217
218 if bare_metal:
219 self = ArmSystem()
220 else:
221 self = LinuxArmSystem()
222
223 if not mdesc:
224 # generic system
225 mdesc = SysConfig()
226
227 self.readfile = mdesc.script()
228 self.iobus = NoncoherentBus()
229 self.membus = MemBus()
230 self.membus.badaddr_responder.warn_access = "warn"
231 self.bridge = Bridge(delay='50ns')
232 self.bridge.master = self.iobus.slave
233 self.bridge.slave = self.membus.master
234
235 self.mem_mode = mem_mode
236
237 if machine_type == "RealView_PBX":
238 self.realview = RealViewPBX()
239 elif machine_type == "RealView_EB":
240 self.realview = RealViewEB()
241 elif machine_type == "VExpress_ELT":
242 self.realview = VExpress_ELT()
243 elif machine_type == "VExpress_EMM":
244 self.realview = VExpress_EMM()
245 self.load_addr_mask = 0xffffffff
246 else:
247 print "Unknown Machine Type"
248 sys.exit(1)
249
250 self.cf0 = CowIdeDisk(driveID='master')
251 self.cf0.childImage(mdesc.disk())
252 # default to an IDE controller rather than a CF one
253 # assuming we've got one
254 try:
255 self.realview.ide.disks = [self.cf0]
256 except:
257 self.realview.cf_ctrl.disks = [self.cf0]
258
259 if bare_metal:
260 # EOT character on UART will end the simulation
261 self.realview.uart.end_on_eot = True
|
276 self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())))
277 self.mem_ranges = [self.physmem.range]
| 262 self.mem_ranges = [AddrRange(mdesc.mem())]
|
278 else:
279 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
280 if dtb_filename is not None:
281 self.dtb_filename = dtb_filename
282 self.machine_type = machine_type
283 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
284 print "The currently selected ARM platforms doesn't support"
285 print " the amount of DRAM you've selected. Please try"
286 print " another platform"
287 sys.exit(1)
288
289 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
290 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
| 263 else:
264 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
265 if dtb_filename is not None:
266 self.dtb_filename = dtb_filename
267 self.machine_type = machine_type
268 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
269 print "The currently selected ARM platforms doesn't support"
270 print " the amount of DRAM you've selected. Please try"
271 print " another platform"
272 sys.exit(1)
273
274 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
275 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
|
291
292 self.physmem = MemClass(range = AddrRange(self.realview.mem_start_addr,
293 size = mdesc.mem()),
294 conf_table_reported = True)
295 self.mem_ranges = [self.physmem.range]
| 276 self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
277 size = mdesc.mem())]
|
296 self.realview.setupBootLoader(self.membus, self, binary)
297 self.gic_cpu_addr = self.realview.gic.cpu_addr
298 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
299
300 if mdesc.disk().lower().count('android'):
301 boot_flags += " init=/init "
302 self.boot_osflags = boot_flags
| 278 self.realview.setupBootLoader(self.membus, self, binary)
279 self.gic_cpu_addr = self.realview.gic.cpu_addr
280 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
281
282 if mdesc.disk().lower().count('android'):
283 boot_flags += " init=/init "
284 self.boot_osflags = boot_flags
|
303
304 self.physmem.port = self.membus.master
| |
305 self.realview.attachOnChipIO(self.membus, self.bridge)
306 self.realview.attachIO(self.iobus)
307 self.intrctrl = IntrControl()
308 self.terminal = Terminal()
309 self.vncserver = VncServer()
310
311 self.system_port = self.membus.slave
312
313 return self
314
315
| 285 self.realview.attachOnChipIO(self.membus, self.bridge)
286 self.realview.attachIO(self.iobus)
287 self.intrctrl = IntrControl()
288 self.terminal = Terminal()
289 self.vncserver = VncServer()
290
291 self.system_port = self.membus.slave
292
293 return self
294
295
|
316def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None):
| 296def makeLinuxMipsSystem(mem_mode, mdesc = None):
|
317 class BaseMalta(Malta):
318 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
319 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
320 pci_func=0, pci_dev=0, pci_bus=0)
321
322 self = LinuxMipsSystem()
323 if not mdesc:
324 # generic system
325 mdesc = SysConfig()
326 self.readfile = mdesc.script()
327 self.iobus = NoncoherentBus()
328 self.membus = MemBus()
329 self.bridge = Bridge(delay='50ns')
| 297 class BaseMalta(Malta):
298 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
299 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
300 pci_func=0, pci_dev=0, pci_bus=0)
301
302 self = LinuxMipsSystem()
303 if not mdesc:
304 # generic system
305 mdesc = SysConfig()
306 self.readfile = mdesc.script()
307 self.iobus = NoncoherentBus()
308 self.membus = MemBus()
309 self.bridge = Bridge(delay='50ns')
|
330 self.physmem = MemClass(range = AddrRange('1GB'))
331 self.mem_ranges = [self.physmem.range]
| 310 self.mem_ranges = [AddrRange('1GB')]
|
332 self.bridge.master = self.iobus.slave
333 self.bridge.slave = self.membus.master
| 311 self.bridge.master = self.iobus.slave
312 self.bridge.slave = self.membus.master
|
334 self.physmem.port = self.membus.master
| |
335 self.disk0 = CowIdeDisk(driveID='master')
336 self.disk2 = CowIdeDisk(driveID='master')
337 self.disk0.childImage(mdesc.disk())
338 self.disk2.childImage(disk('linux-bigswap2.img'))
339 self.malta = BaseMalta()
340 self.malta.attachIO(self.iobus)
341 self.malta.ide.pio = self.iobus.master
342 self.malta.ide.config = self.iobus.master
343 self.malta.ide.dma = self.iobus.slave
344 self.malta.ethernet.pio = self.iobus.master
345 self.malta.ethernet.config = self.iobus.master
346 self.malta.ethernet.dma = self.iobus.slave
347 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
348 read_only = True))
349 self.intrctrl = IntrControl()
350 self.mem_mode = mem_mode
351 self.terminal = Terminal()
352 self.kernel = binary('mips/vmlinux')
353 self.console = binary('mips/console')
354 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
355
356 self.system_port = self.membus.slave
357
358 return self
359
360def x86IOAddress(port):
361 IO_address_space_base = 0x8000000000000000
362 return IO_address_space_base + port
363
364def connectX86ClassicSystem(x86_sys, numCPUs):
365 # Constants similar to x86_traits.hh
366 IO_address_space_base = 0x8000000000000000
367 pci_config_address_space_base = 0xc000000000000000
368 interrupts_address_space_base = 0xa000000000000000
369 APIC_range_size = 1 << 12;
370
371 x86_sys.membus = MemBus()
| 313 self.disk0 = CowIdeDisk(driveID='master')
314 self.disk2 = CowIdeDisk(driveID='master')
315 self.disk0.childImage(mdesc.disk())
316 self.disk2.childImage(disk('linux-bigswap2.img'))
317 self.malta = BaseMalta()
318 self.malta.attachIO(self.iobus)
319 self.malta.ide.pio = self.iobus.master
320 self.malta.ide.config = self.iobus.master
321 self.malta.ide.dma = self.iobus.slave
322 self.malta.ethernet.pio = self.iobus.master
323 self.malta.ethernet.config = self.iobus.master
324 self.malta.ethernet.dma = self.iobus.slave
325 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
326 read_only = True))
327 self.intrctrl = IntrControl()
328 self.mem_mode = mem_mode
329 self.terminal = Terminal()
330 self.kernel = binary('mips/vmlinux')
331 self.console = binary('mips/console')
332 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
333
334 self.system_port = self.membus.slave
335
336 return self
337
338def x86IOAddress(port):
339 IO_address_space_base = 0x8000000000000000
340 return IO_address_space_base + port
341
342def connectX86ClassicSystem(x86_sys, numCPUs):
343 # Constants similar to x86_traits.hh
344 IO_address_space_base = 0x8000000000000000
345 pci_config_address_space_base = 0xc000000000000000
346 interrupts_address_space_base = 0xa000000000000000
347 APIC_range_size = 1 << 12;
348
349 x86_sys.membus = MemBus()
|
372 x86_sys.physmem.port = x86_sys.membus.master
| |
373
374 # North Bridge
375 x86_sys.iobus = NoncoherentBus()
376 x86_sys.bridge = Bridge(delay='50ns')
377 x86_sys.bridge.master = x86_sys.iobus.slave
378 x86_sys.bridge.slave = x86_sys.membus.master
379 # Allow the bridge to pass through the IO APIC (two pages),
380 # everything in the IO address range up to the local APIC, and
381 # then the entire PCI address space and beyond
382 x86_sys.bridge.ranges = \
383 [
384 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
385 x86_sys.pc.south_bridge.io_apic.pio_addr +
386 APIC_range_size - 1),
387 AddrRange(IO_address_space_base,
388 interrupts_address_space_base - 1),
389 AddrRange(pci_config_address_space_base,
390 Addr.max)
391 ]
392
393 # Create a bridge from the IO bus to the memory bus to allow access to
394 # the local APIC (two pages)
395 x86_sys.apicbridge = Bridge(delay='50ns')
396 x86_sys.apicbridge.slave = x86_sys.iobus.master
397 x86_sys.apicbridge.master = x86_sys.membus.slave
398 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
399 interrupts_address_space_base +
400 numCPUs * APIC_range_size
401 - 1)]
402
403 # connect the io bus
404 x86_sys.pc.attachIO(x86_sys.iobus)
405
406 x86_sys.system_port = x86_sys.membus.slave
407
408def connectX86RubySystem(x86_sys):
409 # North Bridge
410 x86_sys.piobus = NoncoherentBus()
411
| 350
351 # North Bridge
352 x86_sys.iobus = NoncoherentBus()
353 x86_sys.bridge = Bridge(delay='50ns')
354 x86_sys.bridge.master = x86_sys.iobus.slave
355 x86_sys.bridge.slave = x86_sys.membus.master
356 # Allow the bridge to pass through the IO APIC (two pages),
357 # everything in the IO address range up to the local APIC, and
358 # then the entire PCI address space and beyond
359 x86_sys.bridge.ranges = \
360 [
361 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
362 x86_sys.pc.south_bridge.io_apic.pio_addr +
363 APIC_range_size - 1),
364 AddrRange(IO_address_space_base,
365 interrupts_address_space_base - 1),
366 AddrRange(pci_config_address_space_base,
367 Addr.max)
368 ]
369
370 # Create a bridge from the IO bus to the memory bus to allow access to
371 # the local APIC (two pages)
372 x86_sys.apicbridge = Bridge(delay='50ns')
373 x86_sys.apicbridge.slave = x86_sys.iobus.master
374 x86_sys.apicbridge.master = x86_sys.membus.slave
375 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
376 interrupts_address_space_base +
377 numCPUs * APIC_range_size
378 - 1)]
379
380 # connect the io bus
381 x86_sys.pc.attachIO(x86_sys.iobus)
382
383 x86_sys.system_port = x86_sys.membus.slave
384
385def connectX86RubySystem(x86_sys):
386 # North Bridge
387 x86_sys.piobus = NoncoherentBus()
388
|
412 #
413 # Pio functional accesses from devices need direct access to memory
414 # RubyPort currently does support functional accesses. Therefore provide
415 # the piobus a direct connection to physical memory
416 #
417 x86_sys.piobus.master = x86_sys.physmem.port
| |
418 # add the ide to the list of dma devices that later need to attach to
419 # dma controllers
420 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
421 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
422
423
| 389 # add the ide to the list of dma devices that later need to attach to
390 # dma controllers
391 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
392 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
393
394
|
424def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None,
| 395def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
|
425 Ruby = False):
426 if self == None:
427 self = X86System()
428
429 if not mdesc:
430 # generic system
431 mdesc = SysConfig()
432 self.readfile = mdesc.script()
433
434 self.mem_mode = mem_mode
435
436 # Physical memory
| 396 Ruby = False):
397 if self == None:
398 self = X86System()
399
400 if not mdesc:
401 # generic system
402 mdesc = SysConfig()
403 self.readfile = mdesc.script()
404
405 self.mem_mode = mem_mode
406
407 # Physical memory
|
437 self.physmem = MemClass(range = AddrRange(mdesc.mem()))
438 self.mem_ranges = [self.physmem.range]
| 408 self.mem_ranges = [AddrRange(mdesc.mem())]
|
439
440 # Platform
441 self.pc = Pc()
442
443 # Create and connect the busses required by each memory system
444 if Ruby:
445 connectX86RubySystem(self)
446 else:
447 connectX86ClassicSystem(self, numCPUs)
448
449 self.intrctrl = IntrControl()
450
451 # Disks
452 disk0 = CowIdeDisk(driveID='master')
453 disk2 = CowIdeDisk(driveID='master')
454 disk0.childImage(mdesc.disk())
455 disk2.childImage(disk('linux-bigswap2.img'))
456 self.pc.south_bridge.ide.disks = [disk0, disk2]
457
458 # Add in a Bios information structure.
459 structures = [X86SMBiosBiosInformation()]
460 self.smbios_table.structures = structures
461
462 # Set up the Intel MP table
463 base_entries = []
464 ext_entries = []
465 for i in xrange(numCPUs):
466 bp = X86IntelMPProcessor(
467 local_apic_id = i,
468 local_apic_version = 0x14,
469 enable = True,
470 bootstrap = (i == 0))
471 base_entries.append(bp)
472 io_apic = X86IntelMPIOAPIC(
473 id = numCPUs,
474 version = 0x11,
475 enable = True,
476 address = 0xfec00000)
477 self.pc.south_bridge.io_apic.apic_id = io_apic.id
478 base_entries.append(io_apic)
479 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
480 base_entries.append(isa_bus)
481 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
482 base_entries.append(pci_bus)
483 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
484 subtractive_decode=True, parent_bus=1)
485 ext_entries.append(connect_busses)
486 pci_dev4_inta = X86IntelMPIOIntAssignment(
487 interrupt_type = 'INT',
488 polarity = 'ConformPolarity',
489 trigger = 'ConformTrigger',
490 source_bus_id = 1,
491 source_bus_irq = 0 + (4 << 2),
492 dest_io_apic_id = io_apic.id,
493 dest_io_apic_intin = 16)
494 base_entries.append(pci_dev4_inta)
495 def assignISAInt(irq, apicPin):
496 assign_8259_to_apic = X86IntelMPIOIntAssignment(
497 interrupt_type = 'ExtInt',
498 polarity = 'ConformPolarity',
499 trigger = 'ConformTrigger',
500 source_bus_id = 0,
501 source_bus_irq = irq,
502 dest_io_apic_id = io_apic.id,
503 dest_io_apic_intin = 0)
504 base_entries.append(assign_8259_to_apic)
505 assign_to_apic = X86IntelMPIOIntAssignment(
506 interrupt_type = 'INT',
507 polarity = 'ConformPolarity',
508 trigger = 'ConformTrigger',
509 source_bus_id = 0,
510 source_bus_irq = irq,
511 dest_io_apic_id = io_apic.id,
512 dest_io_apic_intin = apicPin)
513 base_entries.append(assign_to_apic)
514 assignISAInt(0, 2)
515 assignISAInt(1, 1)
516 for i in range(3, 15):
517 assignISAInt(i, i)
518 self.intel_mp_table.base_entries = base_entries
519 self.intel_mp_table.ext_entries = ext_entries
520
| 409
410 # Platform
411 self.pc = Pc()
412
413 # Create and connect the busses required by each memory system
414 if Ruby:
415 connectX86RubySystem(self)
416 else:
417 connectX86ClassicSystem(self, numCPUs)
418
419 self.intrctrl = IntrControl()
420
421 # Disks
422 disk0 = CowIdeDisk(driveID='master')
423 disk2 = CowIdeDisk(driveID='master')
424 disk0.childImage(mdesc.disk())
425 disk2.childImage(disk('linux-bigswap2.img'))
426 self.pc.south_bridge.ide.disks = [disk0, disk2]
427
428 # Add in a Bios information structure.
429 structures = [X86SMBiosBiosInformation()]
430 self.smbios_table.structures = structures
431
432 # Set up the Intel MP table
433 base_entries = []
434 ext_entries = []
435 for i in xrange(numCPUs):
436 bp = X86IntelMPProcessor(
437 local_apic_id = i,
438 local_apic_version = 0x14,
439 enable = True,
440 bootstrap = (i == 0))
441 base_entries.append(bp)
442 io_apic = X86IntelMPIOAPIC(
443 id = numCPUs,
444 version = 0x11,
445 enable = True,
446 address = 0xfec00000)
447 self.pc.south_bridge.io_apic.apic_id = io_apic.id
448 base_entries.append(io_apic)
449 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
450 base_entries.append(isa_bus)
451 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
452 base_entries.append(pci_bus)
453 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
454 subtractive_decode=True, parent_bus=1)
455 ext_entries.append(connect_busses)
456 pci_dev4_inta = X86IntelMPIOIntAssignment(
457 interrupt_type = 'INT',
458 polarity = 'ConformPolarity',
459 trigger = 'ConformTrigger',
460 source_bus_id = 1,
461 source_bus_irq = 0 + (4 << 2),
462 dest_io_apic_id = io_apic.id,
463 dest_io_apic_intin = 16)
464 base_entries.append(pci_dev4_inta)
465 def assignISAInt(irq, apicPin):
466 assign_8259_to_apic = X86IntelMPIOIntAssignment(
467 interrupt_type = 'ExtInt',
468 polarity = 'ConformPolarity',
469 trigger = 'ConformTrigger',
470 source_bus_id = 0,
471 source_bus_irq = irq,
472 dest_io_apic_id = io_apic.id,
473 dest_io_apic_intin = 0)
474 base_entries.append(assign_8259_to_apic)
475 assign_to_apic = X86IntelMPIOIntAssignment(
476 interrupt_type = 'INT',
477 polarity = 'ConformPolarity',
478 trigger = 'ConformTrigger',
479 source_bus_id = 0,
480 source_bus_irq = irq,
481 dest_io_apic_id = io_apic.id,
482 dest_io_apic_intin = apicPin)
483 base_entries.append(assign_to_apic)
484 assignISAInt(0, 2)
485 assignISAInt(1, 1)
486 for i in range(3, 15):
487 assignISAInt(i, i)
488 self.intel_mp_table.base_entries = base_entries
489 self.intel_mp_table.ext_entries = ext_entries
490
|
521def makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None,
| 491def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
|
522 Ruby = False):
523 self = LinuxX86System()
524
525 # Build up the x86 system and then specialize it for Linux
| 492 Ruby = False):
493 self = LinuxX86System()
494
495 # Build up the x86 system and then specialize it for Linux
|
526 makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby)
| 496 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
|
527
528 # We assume below that there's at least 1MB of memory. We'll require 2
529 # just to avoid corner cases.
| 497
498 # We assume below that there's at least 1MB of memory. We'll require 2
499 # just to avoid corner cases.
|
530 phys_mem_size = sum(map(lambda mem: mem.range.size(),
531 self.memories.unproxy(self)))
| 500 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
|
532 assert(phys_mem_size >= 0x200000)
533
534 self.e820_table.entries = \
535 [
536 # Mark the first megabyte of memory as reserved
537 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
538 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
539 # Mark the rest as available
540 X86E820Entry(addr = 0x100000,
541 size = '%dB' % (phys_mem_size - 0x100000),
542 range_type = 1)
543 ]
544
545 # Command line
546 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
547 'root=/dev/hda1'
548 return self
549
550
551def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
552 self = Root(full_system = full_system)
553 self.testsys = testSystem
554 self.drivesys = driveSystem
555 self.etherlink = EtherLink()
556 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
557 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
558
559 if hasattr(testSystem, 'realview'):
560 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
561 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
562 elif hasattr(testSystem, 'tsunami'):
563 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
564 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
565 else:
566 fatal("Don't know how to connect these system together")
567
568 if dumpfile:
569 self.etherdump = EtherDump(file=dumpfile)
570 self.etherlink.dump = Parent.etherdump
571
572 return self
| 501 assert(phys_mem_size >= 0x200000)
502
503 self.e820_table.entries = \
504 [
505 # Mark the first megabyte of memory as reserved
506 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
507 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
508 # Mark the rest as available
509 X86E820Entry(addr = 0x100000,
510 size = '%dB' % (phys_mem_size - 0x100000),
511 range_type = 1)
512 ]
513
514 # Command line
515 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
516 'root=/dev/hda1'
517 return self
518
519
520def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
521 self = Root(full_system = full_system)
522 self.testsys = testSystem
523 self.drivesys = driveSystem
524 self.etherlink = EtherLink()
525 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
526 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
527
528 if hasattr(testSystem, 'realview'):
529 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
530 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
531 elif hasattr(testSystem, 'tsunami'):
532 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
533 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
534 else:
535 fatal("Don't know how to connect these system together")
536
537 if dumpfile:
538 self.etherdump = EtherDump(file=dumpfile)
539 self.etherlink.dump = Parent.etherdump
540
541 return self
|