1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47 image = CowDiskImage(child=RawDiskImage(read_only=True),
48 read_only=False)
49
50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59 IO_address_space_base = 0x80000000000
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
76 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
77 self.bridge.master = self.iobus.slave
78 self.bridge.slave = self.membus.master
79 self.physmem.port = self.membus.master
80 self.disk0 = CowIdeDisk(driveID='master')
81 self.disk2 = CowIdeDisk(driveID='master')
82 self.disk0.childImage(mdesc.disk())
83 self.disk2.childImage(disk('linux-bigswap2.img'))
84 self.tsunami = BaseTsunami()
85 self.tsunami.attachIO(self.iobus)
86 self.tsunami.ide.pio = self.iobus.master
87 self.tsunami.ide.config = self.iobus.master
88 self.tsunami.ide.dma = self.iobus.slave
89 self.tsunami.ethernet.pio = self.iobus.master
90 self.tsunami.ethernet.config = self.iobus.master
91 self.tsunami.ethernet.dma = self.iobus.slave
92 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
93 read_only = True))
94 self.intrctrl = IntrControl()
95 self.mem_mode = mem_mode
96 self.terminal = Terminal()
97 self.kernel = binary('vmlinux')
98 self.pal = binary('ts_osfpal')
99 self.console = binary('console')
100 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
101
102 self.system_port = self.membus.slave
103
104 return self
105
106def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
107 class BaseTsunami(Tsunami):
108 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
109 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
110 pci_func=0, pci_dev=0, pci_bus=0)
111
112 physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
113 self = LinuxAlphaSystem(physmem = physmem)
114 if not mdesc:
115 # generic system
116 mdesc = SysConfig()
117 self.readfile = mdesc.script()
118
119 # Create pio bus to connect all device pio ports to rubymem's pio port
120 self.piobus = NoncoherentBus()
121
122 #
123 # Pio functional accesses from devices need direct access to memory
124 # RubyPort currently does support functional accesses. Therefore provide
125 # the piobus a direct connection to physical memory
126 #
127 self.piobus.master = physmem.port
128
129 self.disk0 = CowIdeDisk(driveID='master')
130 self.disk2 = CowIdeDisk(driveID='master')
131 self.disk0.childImage(mdesc.disk())
132 self.disk2.childImage(disk('linux-bigswap2.img'))
133 self.tsunami = BaseTsunami()
134 self.tsunami.attachIO(self.piobus)
135 self.tsunami.ide.pio = self.piobus.master
136 self.tsunami.ide.config = self.piobus.master
137 self.tsunami.ethernet.pio = self.piobus.master
138 self.tsunami.ethernet.config = self.piobus.master
139
140 #
141 # Store the dma devices for later connection to dma ruby ports.
142 # Append an underscore to dma_devices to avoid the SimObjectVector check.
143 #
144 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
145
146 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
147 read_only = True))
148 self.intrctrl = IntrControl()
149 self.mem_mode = mem_mode
150 self.terminal = Terminal()
151 self.kernel = binary('vmlinux')
152 self.pal = binary('ts_osfpal')
153 self.console = binary('console')
154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
155
156 return self
157
158def makeSparcSystem(mem_mode, mdesc = None):
159 # Constants from iob.cc and uart8250.cc
160 iob_man_addr = 0x9800000000
161 uart_pio_size = 8
162
163 class CowMmDisk(MmDisk):
164 image = CowDiskImage(child=RawDiskImage(read_only=True),
165 read_only=False)
166
167 def childImage(self, ci):
168 self.image.child.image_file = ci
169
170 self = SparcSystem()
171 if not mdesc:
172 # generic system
173 mdesc = SysConfig()
174 self.readfile = mdesc.script()
175 self.iobus = NoncoherentBus()
176 self.membus = MemBus()
177 self.bridge = Bridge(delay='50ns')
178 self.t1000 = T1000()
179 self.t1000.attachOnChipIO(self.membus)
180 self.t1000.attachIO(self.iobus)
181 self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'),
182 zero = True)
183 self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'),
184 zero = True)
185 self.bridge.master = self.iobus.slave
186 self.bridge.slave = self.membus.master
187 self.physmem.port = self.membus.master
188 self.physmem2.port = self.membus.master
189 self.rom.port = self.membus.master
190 self.nvram.port = self.membus.master
191 self.hypervisor_desc.port = self.membus.master
192 self.partition_desc.port = self.membus.master
193 self.intrctrl = IntrControl()
194 self.disk0 = CowMmDisk()
195 self.disk0.childImage(disk('disk.s10hw2'))
196 self.disk0.pio = self.iobus.master
197
198 # The puart0 and hvuart are placed on the IO bus, so create ranges
199 # for them. The remaining IO range is rather fragmented, so poke
200 # holes for the iob and partition descriptors etc.
201 self.bridge.ranges = \
202 [
203 AddrRange(self.t1000.puart0.pio_addr,
204 self.t1000.puart0.pio_addr + uart_pio_size - 1),
205 AddrRange(self.disk0.pio_addr,
206 self.t1000.fake_jbi.pio_addr +
207 self.t1000.fake_jbi.pio_size - 1),
208 AddrRange(self.t1000.fake_clk.pio_addr,
209 iob_man_addr - 1),
210 AddrRange(self.t1000.fake_l2_1.pio_addr,
211 self.t1000.fake_ssi.pio_addr +
212 self.t1000.fake_ssi.pio_size - 1),
213 AddrRange(self.t1000.hvuart.pio_addr,
214 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
215 ]
216 self.reset_bin = binary('reset_new.bin')
217 self.hypervisor_bin = binary('q_new.bin')
218 self.openboot_bin = binary('openboot_new.bin')
219 self.nvram_bin = binary('nvram1')
220 self.hypervisor_desc_bin = binary('1up-hv.bin')
221 self.partition_desc_bin = binary('1up-md.bin')
222
223 self.system_port = self.membus.slave
224
225 return self
226
227def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
228 assert machine_type
229
230 if bare_metal:
231 self = ArmSystem()
232 else:
233 self = LinuxArmSystem()
234
235 if not mdesc:
236 # generic system
237 mdesc = SysConfig()
238
239 self.readfile = mdesc.script()
240 self.iobus = NoncoherentBus()
241 self.membus = MemBus()
242 self.membus.badaddr_responder.warn_access = "warn"
243 self.bridge = Bridge(delay='50ns')
244 self.bridge.master = self.iobus.slave
245 self.bridge.slave = self.membus.master
246
247 self.mem_mode = mem_mode
248
249 if machine_type == "RealView_PBX":
250 self.realview = RealViewPBX()
251 elif machine_type == "RealView_EB":
252 self.realview = RealViewEB()
253 elif machine_type == "VExpress_ELT":
254 self.realview = VExpress_ELT()
255 elif machine_type == "VExpress_EMM":
256 self.realview = VExpress_EMM()
257 self.load_addr_mask = 0xffffffff
258 else:
259 print "Unknown Machine Type"
260 sys.exit(1)
261
262 self.cf0 = CowIdeDisk(driveID='master')
263 self.cf0.childImage(mdesc.disk())
264 # default to an IDE controller rather than a CF one
265 # assuming we've got one
266 try:
267 self.realview.ide.disks = [self.cf0]
268 except:
269 self.realview.cf_ctrl.disks = [self.cf0]
270
271 if bare_metal:
272 # EOT character on UART will end the simulation
273 self.realview.uart.end_on_eot = True
274 self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())),
275 zero = True)
276 else:
277 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
278 self.machine_type = machine_type
279 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
280 print "The currently selected ARM platforms doesn't support"
281 print " the amount of DRAM you've selected. Please try"
282 print " another platform"
283 sys.exit(1)
284
285 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
286 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
287
288 self.physmem = SimpleMemory(range =
289 AddrRange(self.realview.mem_start_addr,
290 size = mdesc.mem()),
291 conf_table_reported = True)
292 self.realview.setupBootLoader(self.membus, self, binary)
293 self.gic_cpu_addr = self.realview.gic.cpu_addr
294 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
295
296 if mdesc.disk().lower().count('android'):
297 boot_flags += " init=/init "
298 self.boot_osflags = boot_flags
299
300 self.physmem.port = self.membus.master
301 self.realview.attachOnChipIO(self.membus, self.bridge)
302 self.realview.attachIO(self.iobus)
303 self.intrctrl = IntrControl()
304 self.terminal = Terminal()
305 self.vncserver = VncServer()
306
307 self.system_port = self.membus.slave
308
309 return self
310
311
312def makeLinuxMipsSystem(mem_mode, mdesc = None):
313 class BaseMalta(Malta):
314 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
315 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
316 pci_func=0, pci_dev=0, pci_bus=0)
317
318 self = LinuxMipsSystem()
319 if not mdesc:
320 # generic system
321 mdesc = SysConfig()
322 self.readfile = mdesc.script()
323 self.iobus = NoncoherentBus()
324 self.membus = MemBus()
325 self.bridge = Bridge(delay='50ns')
326 self.physmem = SimpleMemory(range = AddrRange('1GB'))
327 self.bridge.master = self.iobus.slave
328 self.bridge.slave = self.membus.master
329 self.physmem.port = self.membus.master
330 self.disk0 = CowIdeDisk(driveID='master')
331 self.disk2 = CowIdeDisk(driveID='master')
332 self.disk0.childImage(mdesc.disk())
333 self.disk2.childImage(disk('linux-bigswap2.img'))
334 self.malta = BaseMalta()
335 self.malta.attachIO(self.iobus)
336 self.malta.ide.pio = self.iobus.master
337 self.malta.ide.config = self.iobus.master
338 self.malta.ide.dma = self.iobus.slave
339 self.malta.ethernet.pio = self.iobus.master
340 self.malta.ethernet.config = self.iobus.master
341 self.malta.ethernet.dma = self.iobus.slave
342 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
343 read_only = True))
344 self.intrctrl = IntrControl()
345 self.mem_mode = mem_mode
346 self.terminal = Terminal()
347 self.kernel = binary('mips/vmlinux')
348 self.console = binary('mips/console')
349 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
350
351 self.system_port = self.membus.slave
352
353 return self
354
355def x86IOAddress(port):
356 IO_address_space_base = 0x8000000000000000
357 return IO_address_space_base + port
358
359def connectX86ClassicSystem(x86_sys, numCPUs):
360 # Constants similar to x86_traits.hh
361 IO_address_space_base = 0x8000000000000000
362 pci_config_address_space_base = 0xc000000000000000
363 interrupts_address_space_base = 0xa000000000000000
364 APIC_range_size = 1 << 12;
365
366 x86_sys.membus = MemBus()
367 x86_sys.physmem.port = x86_sys.membus.master
368
369 # North Bridge
370 x86_sys.iobus = NoncoherentBus()
371 x86_sys.bridge = Bridge(delay='50ns')
372 x86_sys.bridge.master = x86_sys.iobus.slave
373 x86_sys.bridge.slave = x86_sys.membus.master
374 # Allow the bridge to pass through the IO APIC (two pages),
375 # everything in the IO address range up to the local APIC, and
376 # then the entire PCI address space and beyond
377 x86_sys.bridge.ranges = \
378 [
379 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
380 x86_sys.pc.south_bridge.io_apic.pio_addr +
381 APIC_range_size - 1),
382 AddrRange(IO_address_space_base,
383 interrupts_address_space_base - 1),
384 AddrRange(pci_config_address_space_base,
385 Addr.max)
386 ]
387
388 # Create a bridge from the IO bus to the memory bus to allow access to
389 # the local APIC (two pages)
390 x86_sys.apicbridge = Bridge(delay='50ns')
391 x86_sys.apicbridge.slave = x86_sys.iobus.master
392 x86_sys.apicbridge.master = x86_sys.membus.slave
393 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
394 interrupts_address_space_base +
395 numCPUs * APIC_range_size
396 - 1)]
397
398 # connect the io bus
399 x86_sys.pc.attachIO(x86_sys.iobus)
400
401 x86_sys.system_port = x86_sys.membus.slave
402
403def connectX86RubySystem(x86_sys):
404 # North Bridge
405 x86_sys.piobus = NoncoherentBus()
406
407 #
408 # Pio functional accesses from devices need direct access to memory
409 # RubyPort currently does support functional accesses. Therefore provide
410 # the piobus a direct connection to physical memory
411 #
412 x86_sys.piobus.master = x86_sys.physmem.port
413 # add the ide to the list of dma devices that later need to attach to
414 # dma controllers
415 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
416 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
417
418
419def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
420 if self == None:
421 self = X86System()
422
423 if not mdesc:
424 # generic system
425 mdesc = SysConfig()
426 self.readfile = mdesc.script()
427
428 self.mem_mode = mem_mode
429
430 # Physical memory
431 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
432
433 # Platform
434 self.pc = Pc()
435
436 # Create and connect the busses required by each memory system
437 if Ruby:
438 connectX86RubySystem(self)
439 else:
440 connectX86ClassicSystem(self, numCPUs)
441
442 self.intrctrl = IntrControl()
443
444 # Disks
445 disk0 = CowIdeDisk(driveID='master')
446 disk2 = CowIdeDisk(driveID='master')
447 disk0.childImage(mdesc.disk())
448 disk2.childImage(disk('linux-bigswap2.img'))
449 self.pc.south_bridge.ide.disks = [disk0, disk2]
450
451 # Add in a Bios information structure.
452 structures = [X86SMBiosBiosInformation()]
453 self.smbios_table.structures = structures
454
455 # Set up the Intel MP table
456 base_entries = []
457 ext_entries = []
458 for i in xrange(numCPUs):
459 bp = X86IntelMPProcessor(
460 local_apic_id = i,
461 local_apic_version = 0x14,
462 enable = True,
463 bootstrap = (i == 0))
464 base_entries.append(bp)
465 io_apic = X86IntelMPIOAPIC(
466 id = numCPUs,
467 version = 0x11,
468 enable = True,
469 address = 0xfec00000)
470 self.pc.south_bridge.io_apic.apic_id = io_apic.id
471 base_entries.append(io_apic)
472 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
473 base_entries.append(isa_bus)
474 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
475 base_entries.append(pci_bus)
476 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
477 subtractive_decode=True, parent_bus=1)
478 ext_entries.append(connect_busses)
479 pci_dev4_inta = X86IntelMPIOIntAssignment(
480 interrupt_type = 'INT',
481 polarity = 'ConformPolarity',
482 trigger = 'ConformTrigger',
483 source_bus_id = 1,
484 source_bus_irq = 0 + (4 << 2),
485 dest_io_apic_id = io_apic.id,
486 dest_io_apic_intin = 16)
487 base_entries.append(pci_dev4_inta)
488 def assignISAInt(irq, apicPin):
489 assign_8259_to_apic = X86IntelMPIOIntAssignment(
490 interrupt_type = 'ExtInt',
491 polarity = 'ConformPolarity',
492 trigger = 'ConformTrigger',
493 source_bus_id = 0,
494 source_bus_irq = irq,
495 dest_io_apic_id = io_apic.id,
496 dest_io_apic_intin = 0)
497 base_entries.append(assign_8259_to_apic)
498 assign_to_apic = X86IntelMPIOIntAssignment(
499 interrupt_type = 'INT',
500 polarity = 'ConformPolarity',
501 trigger = 'ConformTrigger',
502 source_bus_id = 0,
503 source_bus_irq = irq,
504 dest_io_apic_id = io_apic.id,
505 dest_io_apic_intin = apicPin)
506 base_entries.append(assign_to_apic)
507 assignISAInt(0, 2)
508 assignISAInt(1, 1)
509 for i in range(3, 15):
510 assignISAInt(i, i)
511 self.intel_mp_table.base_entries = base_entries
512 self.intel_mp_table.ext_entries = ext_entries
513
514def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
515 self = LinuxX86System()
516
517 # Build up the x86 system and then specialize it for Linux
518 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
519
520 # We assume below that there's at least 1MB of memory. We'll require 2
521 # just to avoid corner cases.
| 1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47 image = CowDiskImage(child=RawDiskImage(read_only=True),
48 read_only=False)
49
50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59 IO_address_space_base = 0x80000000000
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
76 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
77 self.bridge.master = self.iobus.slave
78 self.bridge.slave = self.membus.master
79 self.physmem.port = self.membus.master
80 self.disk0 = CowIdeDisk(driveID='master')
81 self.disk2 = CowIdeDisk(driveID='master')
82 self.disk0.childImage(mdesc.disk())
83 self.disk2.childImage(disk('linux-bigswap2.img'))
84 self.tsunami = BaseTsunami()
85 self.tsunami.attachIO(self.iobus)
86 self.tsunami.ide.pio = self.iobus.master
87 self.tsunami.ide.config = self.iobus.master
88 self.tsunami.ide.dma = self.iobus.slave
89 self.tsunami.ethernet.pio = self.iobus.master
90 self.tsunami.ethernet.config = self.iobus.master
91 self.tsunami.ethernet.dma = self.iobus.slave
92 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
93 read_only = True))
94 self.intrctrl = IntrControl()
95 self.mem_mode = mem_mode
96 self.terminal = Terminal()
97 self.kernel = binary('vmlinux')
98 self.pal = binary('ts_osfpal')
99 self.console = binary('console')
100 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
101
102 self.system_port = self.membus.slave
103
104 return self
105
106def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
107 class BaseTsunami(Tsunami):
108 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
109 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
110 pci_func=0, pci_dev=0, pci_bus=0)
111
112 physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
113 self = LinuxAlphaSystem(physmem = physmem)
114 if not mdesc:
115 # generic system
116 mdesc = SysConfig()
117 self.readfile = mdesc.script()
118
119 # Create pio bus to connect all device pio ports to rubymem's pio port
120 self.piobus = NoncoherentBus()
121
122 #
123 # Pio functional accesses from devices need direct access to memory
124 # RubyPort currently does support functional accesses. Therefore provide
125 # the piobus a direct connection to physical memory
126 #
127 self.piobus.master = physmem.port
128
129 self.disk0 = CowIdeDisk(driveID='master')
130 self.disk2 = CowIdeDisk(driveID='master')
131 self.disk0.childImage(mdesc.disk())
132 self.disk2.childImage(disk('linux-bigswap2.img'))
133 self.tsunami = BaseTsunami()
134 self.tsunami.attachIO(self.piobus)
135 self.tsunami.ide.pio = self.piobus.master
136 self.tsunami.ide.config = self.piobus.master
137 self.tsunami.ethernet.pio = self.piobus.master
138 self.tsunami.ethernet.config = self.piobus.master
139
140 #
141 # Store the dma devices for later connection to dma ruby ports.
142 # Append an underscore to dma_devices to avoid the SimObjectVector check.
143 #
144 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
145
146 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
147 read_only = True))
148 self.intrctrl = IntrControl()
149 self.mem_mode = mem_mode
150 self.terminal = Terminal()
151 self.kernel = binary('vmlinux')
152 self.pal = binary('ts_osfpal')
153 self.console = binary('console')
154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
155
156 return self
157
158def makeSparcSystem(mem_mode, mdesc = None):
159 # Constants from iob.cc and uart8250.cc
160 iob_man_addr = 0x9800000000
161 uart_pio_size = 8
162
163 class CowMmDisk(MmDisk):
164 image = CowDiskImage(child=RawDiskImage(read_only=True),
165 read_only=False)
166
167 def childImage(self, ci):
168 self.image.child.image_file = ci
169
170 self = SparcSystem()
171 if not mdesc:
172 # generic system
173 mdesc = SysConfig()
174 self.readfile = mdesc.script()
175 self.iobus = NoncoherentBus()
176 self.membus = MemBus()
177 self.bridge = Bridge(delay='50ns')
178 self.t1000 = T1000()
179 self.t1000.attachOnChipIO(self.membus)
180 self.t1000.attachIO(self.iobus)
181 self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'),
182 zero = True)
183 self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'),
184 zero = True)
185 self.bridge.master = self.iobus.slave
186 self.bridge.slave = self.membus.master
187 self.physmem.port = self.membus.master
188 self.physmem2.port = self.membus.master
189 self.rom.port = self.membus.master
190 self.nvram.port = self.membus.master
191 self.hypervisor_desc.port = self.membus.master
192 self.partition_desc.port = self.membus.master
193 self.intrctrl = IntrControl()
194 self.disk0 = CowMmDisk()
195 self.disk0.childImage(disk('disk.s10hw2'))
196 self.disk0.pio = self.iobus.master
197
198 # The puart0 and hvuart are placed on the IO bus, so create ranges
199 # for them. The remaining IO range is rather fragmented, so poke
200 # holes for the iob and partition descriptors etc.
201 self.bridge.ranges = \
202 [
203 AddrRange(self.t1000.puart0.pio_addr,
204 self.t1000.puart0.pio_addr + uart_pio_size - 1),
205 AddrRange(self.disk0.pio_addr,
206 self.t1000.fake_jbi.pio_addr +
207 self.t1000.fake_jbi.pio_size - 1),
208 AddrRange(self.t1000.fake_clk.pio_addr,
209 iob_man_addr - 1),
210 AddrRange(self.t1000.fake_l2_1.pio_addr,
211 self.t1000.fake_ssi.pio_addr +
212 self.t1000.fake_ssi.pio_size - 1),
213 AddrRange(self.t1000.hvuart.pio_addr,
214 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
215 ]
216 self.reset_bin = binary('reset_new.bin')
217 self.hypervisor_bin = binary('q_new.bin')
218 self.openboot_bin = binary('openboot_new.bin')
219 self.nvram_bin = binary('nvram1')
220 self.hypervisor_desc_bin = binary('1up-hv.bin')
221 self.partition_desc_bin = binary('1up-md.bin')
222
223 self.system_port = self.membus.slave
224
225 return self
226
227def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
228 assert machine_type
229
230 if bare_metal:
231 self = ArmSystem()
232 else:
233 self = LinuxArmSystem()
234
235 if not mdesc:
236 # generic system
237 mdesc = SysConfig()
238
239 self.readfile = mdesc.script()
240 self.iobus = NoncoherentBus()
241 self.membus = MemBus()
242 self.membus.badaddr_responder.warn_access = "warn"
243 self.bridge = Bridge(delay='50ns')
244 self.bridge.master = self.iobus.slave
245 self.bridge.slave = self.membus.master
246
247 self.mem_mode = mem_mode
248
249 if machine_type == "RealView_PBX":
250 self.realview = RealViewPBX()
251 elif machine_type == "RealView_EB":
252 self.realview = RealViewEB()
253 elif machine_type == "VExpress_ELT":
254 self.realview = VExpress_ELT()
255 elif machine_type == "VExpress_EMM":
256 self.realview = VExpress_EMM()
257 self.load_addr_mask = 0xffffffff
258 else:
259 print "Unknown Machine Type"
260 sys.exit(1)
261
262 self.cf0 = CowIdeDisk(driveID='master')
263 self.cf0.childImage(mdesc.disk())
264 # default to an IDE controller rather than a CF one
265 # assuming we've got one
266 try:
267 self.realview.ide.disks = [self.cf0]
268 except:
269 self.realview.cf_ctrl.disks = [self.cf0]
270
271 if bare_metal:
272 # EOT character on UART will end the simulation
273 self.realview.uart.end_on_eot = True
274 self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())),
275 zero = True)
276 else:
277 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
278 self.machine_type = machine_type
279 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
280 print "The currently selected ARM platforms doesn't support"
281 print " the amount of DRAM you've selected. Please try"
282 print " another platform"
283 sys.exit(1)
284
285 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
286 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
287
288 self.physmem = SimpleMemory(range =
289 AddrRange(self.realview.mem_start_addr,
290 size = mdesc.mem()),
291 conf_table_reported = True)
292 self.realview.setupBootLoader(self.membus, self, binary)
293 self.gic_cpu_addr = self.realview.gic.cpu_addr
294 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
295
296 if mdesc.disk().lower().count('android'):
297 boot_flags += " init=/init "
298 self.boot_osflags = boot_flags
299
300 self.physmem.port = self.membus.master
301 self.realview.attachOnChipIO(self.membus, self.bridge)
302 self.realview.attachIO(self.iobus)
303 self.intrctrl = IntrControl()
304 self.terminal = Terminal()
305 self.vncserver = VncServer()
306
307 self.system_port = self.membus.slave
308
309 return self
310
311
312def makeLinuxMipsSystem(mem_mode, mdesc = None):
313 class BaseMalta(Malta):
314 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
315 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
316 pci_func=0, pci_dev=0, pci_bus=0)
317
318 self = LinuxMipsSystem()
319 if not mdesc:
320 # generic system
321 mdesc = SysConfig()
322 self.readfile = mdesc.script()
323 self.iobus = NoncoherentBus()
324 self.membus = MemBus()
325 self.bridge = Bridge(delay='50ns')
326 self.physmem = SimpleMemory(range = AddrRange('1GB'))
327 self.bridge.master = self.iobus.slave
328 self.bridge.slave = self.membus.master
329 self.physmem.port = self.membus.master
330 self.disk0 = CowIdeDisk(driveID='master')
331 self.disk2 = CowIdeDisk(driveID='master')
332 self.disk0.childImage(mdesc.disk())
333 self.disk2.childImage(disk('linux-bigswap2.img'))
334 self.malta = BaseMalta()
335 self.malta.attachIO(self.iobus)
336 self.malta.ide.pio = self.iobus.master
337 self.malta.ide.config = self.iobus.master
338 self.malta.ide.dma = self.iobus.slave
339 self.malta.ethernet.pio = self.iobus.master
340 self.malta.ethernet.config = self.iobus.master
341 self.malta.ethernet.dma = self.iobus.slave
342 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
343 read_only = True))
344 self.intrctrl = IntrControl()
345 self.mem_mode = mem_mode
346 self.terminal = Terminal()
347 self.kernel = binary('mips/vmlinux')
348 self.console = binary('mips/console')
349 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
350
351 self.system_port = self.membus.slave
352
353 return self
354
355def x86IOAddress(port):
356 IO_address_space_base = 0x8000000000000000
357 return IO_address_space_base + port
358
359def connectX86ClassicSystem(x86_sys, numCPUs):
360 # Constants similar to x86_traits.hh
361 IO_address_space_base = 0x8000000000000000
362 pci_config_address_space_base = 0xc000000000000000
363 interrupts_address_space_base = 0xa000000000000000
364 APIC_range_size = 1 << 12;
365
366 x86_sys.membus = MemBus()
367 x86_sys.physmem.port = x86_sys.membus.master
368
369 # North Bridge
370 x86_sys.iobus = NoncoherentBus()
371 x86_sys.bridge = Bridge(delay='50ns')
372 x86_sys.bridge.master = x86_sys.iobus.slave
373 x86_sys.bridge.slave = x86_sys.membus.master
374 # Allow the bridge to pass through the IO APIC (two pages),
375 # everything in the IO address range up to the local APIC, and
376 # then the entire PCI address space and beyond
377 x86_sys.bridge.ranges = \
378 [
379 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
380 x86_sys.pc.south_bridge.io_apic.pio_addr +
381 APIC_range_size - 1),
382 AddrRange(IO_address_space_base,
383 interrupts_address_space_base - 1),
384 AddrRange(pci_config_address_space_base,
385 Addr.max)
386 ]
387
388 # Create a bridge from the IO bus to the memory bus to allow access to
389 # the local APIC (two pages)
390 x86_sys.apicbridge = Bridge(delay='50ns')
391 x86_sys.apicbridge.slave = x86_sys.iobus.master
392 x86_sys.apicbridge.master = x86_sys.membus.slave
393 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
394 interrupts_address_space_base +
395 numCPUs * APIC_range_size
396 - 1)]
397
398 # connect the io bus
399 x86_sys.pc.attachIO(x86_sys.iobus)
400
401 x86_sys.system_port = x86_sys.membus.slave
402
403def connectX86RubySystem(x86_sys):
404 # North Bridge
405 x86_sys.piobus = NoncoherentBus()
406
407 #
408 # Pio functional accesses from devices need direct access to memory
409 # RubyPort currently does support functional accesses. Therefore provide
410 # the piobus a direct connection to physical memory
411 #
412 x86_sys.piobus.master = x86_sys.physmem.port
413 # add the ide to the list of dma devices that later need to attach to
414 # dma controllers
415 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
416 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
417
418
419def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
420 if self == None:
421 self = X86System()
422
423 if not mdesc:
424 # generic system
425 mdesc = SysConfig()
426 self.readfile = mdesc.script()
427
428 self.mem_mode = mem_mode
429
430 # Physical memory
431 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
432
433 # Platform
434 self.pc = Pc()
435
436 # Create and connect the busses required by each memory system
437 if Ruby:
438 connectX86RubySystem(self)
439 else:
440 connectX86ClassicSystem(self, numCPUs)
441
442 self.intrctrl = IntrControl()
443
444 # Disks
445 disk0 = CowIdeDisk(driveID='master')
446 disk2 = CowIdeDisk(driveID='master')
447 disk0.childImage(mdesc.disk())
448 disk2.childImage(disk('linux-bigswap2.img'))
449 self.pc.south_bridge.ide.disks = [disk0, disk2]
450
451 # Add in a Bios information structure.
452 structures = [X86SMBiosBiosInformation()]
453 self.smbios_table.structures = structures
454
455 # Set up the Intel MP table
456 base_entries = []
457 ext_entries = []
458 for i in xrange(numCPUs):
459 bp = X86IntelMPProcessor(
460 local_apic_id = i,
461 local_apic_version = 0x14,
462 enable = True,
463 bootstrap = (i == 0))
464 base_entries.append(bp)
465 io_apic = X86IntelMPIOAPIC(
466 id = numCPUs,
467 version = 0x11,
468 enable = True,
469 address = 0xfec00000)
470 self.pc.south_bridge.io_apic.apic_id = io_apic.id
471 base_entries.append(io_apic)
472 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
473 base_entries.append(isa_bus)
474 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
475 base_entries.append(pci_bus)
476 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
477 subtractive_decode=True, parent_bus=1)
478 ext_entries.append(connect_busses)
479 pci_dev4_inta = X86IntelMPIOIntAssignment(
480 interrupt_type = 'INT',
481 polarity = 'ConformPolarity',
482 trigger = 'ConformTrigger',
483 source_bus_id = 1,
484 source_bus_irq = 0 + (4 << 2),
485 dest_io_apic_id = io_apic.id,
486 dest_io_apic_intin = 16)
487 base_entries.append(pci_dev4_inta)
488 def assignISAInt(irq, apicPin):
489 assign_8259_to_apic = X86IntelMPIOIntAssignment(
490 interrupt_type = 'ExtInt',
491 polarity = 'ConformPolarity',
492 trigger = 'ConformTrigger',
493 source_bus_id = 0,
494 source_bus_irq = irq,
495 dest_io_apic_id = io_apic.id,
496 dest_io_apic_intin = 0)
497 base_entries.append(assign_8259_to_apic)
498 assign_to_apic = X86IntelMPIOIntAssignment(
499 interrupt_type = 'INT',
500 polarity = 'ConformPolarity',
501 trigger = 'ConformTrigger',
502 source_bus_id = 0,
503 source_bus_irq = irq,
504 dest_io_apic_id = io_apic.id,
505 dest_io_apic_intin = apicPin)
506 base_entries.append(assign_to_apic)
507 assignISAInt(0, 2)
508 assignISAInt(1, 1)
509 for i in range(3, 15):
510 assignISAInt(i, i)
511 self.intel_mp_table.base_entries = base_entries
512 self.intel_mp_table.ext_entries = ext_entries
513
514def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
515 self = LinuxX86System()
516
517 # Build up the x86 system and then specialize it for Linux
518 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
519
520 # We assume below that there's at least 1MB of memory. We'll require 2
521 # just to avoid corner cases.
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