1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29from m5.objects import *
30from Benchmarks import *
31
32class CowIdeDisk(IdeDisk):
33 image = CowDiskImage(child=RawDiskImage(read_only=True),
34 read_only=False)
35
36 def childImage(self, ci):
37 self.image.child.image_file = ci
38
39class MemBus(Bus):
40 badaddr_responder = BadAddr()
41 default = Self.badaddr_responder.pio
42
43
44def makeLinuxAlphaSystem(mem_mode, mdesc = None):
45 class BaseTsunami(Tsunami):
46 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
47 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
48 pci_func=0, pci_dev=0, pci_bus=0)
49
50 self = LinuxAlphaSystem()
51 if not mdesc:
52 # generic system
53 mdesc = SysConfig()
54 self.readfile = mdesc.script()
55 self.iobus = Bus(bus_id=0)
56 self.membus = MemBus(bus_id=1)
57 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
58 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
59 self.bridge.side_a = self.iobus.port
60 self.bridge.side_b = self.membus.port
61 self.physmem.port = self.membus.port
62 self.disk0 = CowIdeDisk(driveID='master')
63 self.disk2 = CowIdeDisk(driveID='master')
64 self.disk0.childImage(mdesc.disk())
65 self.disk2.childImage(disk('linux-bigswap2.img'))
66 self.tsunami = BaseTsunami()
67 self.tsunami.attachIO(self.iobus)
68 self.tsunami.ide.pio = self.iobus.port
69 self.tsunami.ethernet.pio = self.iobus.port
70 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
71 read_only = True))
72 self.intrctrl = IntrControl()
73 self.mem_mode = mem_mode
74 self.terminal = Terminal()
75 self.kernel = binary('vmlinux')
76 self.pal = binary('ts_osfpal')
77 self.console = binary('console')
78 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
79
80 return self
81
| 1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29from m5.objects import *
30from Benchmarks import *
31
32class CowIdeDisk(IdeDisk):
33 image = CowDiskImage(child=RawDiskImage(read_only=True),
34 read_only=False)
35
36 def childImage(self, ci):
37 self.image.child.image_file = ci
38
39class MemBus(Bus):
40 badaddr_responder = BadAddr()
41 default = Self.badaddr_responder.pio
42
43
44def makeLinuxAlphaSystem(mem_mode, mdesc = None):
45 class BaseTsunami(Tsunami):
46 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
47 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
48 pci_func=0, pci_dev=0, pci_bus=0)
49
50 self = LinuxAlphaSystem()
51 if not mdesc:
52 # generic system
53 mdesc = SysConfig()
54 self.readfile = mdesc.script()
55 self.iobus = Bus(bus_id=0)
56 self.membus = MemBus(bus_id=1)
57 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
58 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
59 self.bridge.side_a = self.iobus.port
60 self.bridge.side_b = self.membus.port
61 self.physmem.port = self.membus.port
62 self.disk0 = CowIdeDisk(driveID='master')
63 self.disk2 = CowIdeDisk(driveID='master')
64 self.disk0.childImage(mdesc.disk())
65 self.disk2.childImage(disk('linux-bigswap2.img'))
66 self.tsunami = BaseTsunami()
67 self.tsunami.attachIO(self.iobus)
68 self.tsunami.ide.pio = self.iobus.port
69 self.tsunami.ethernet.pio = self.iobus.port
70 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
71 read_only = True))
72 self.intrctrl = IntrControl()
73 self.mem_mode = mem_mode
74 self.terminal = Terminal()
75 self.kernel = binary('vmlinux')
76 self.pal = binary('ts_osfpal')
77 self.console = binary('console')
78 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
79
80 return self
81
|
82def makeSparcSystem(mem_mode, mdesc = None):
83 class CowMmDisk(MmDisk):
84 image = CowDiskImage(child=RawDiskImage(read_only=True),
85 read_only=False)
86
87 def childImage(self, ci):
88 self.image.child.image_file = ci
89
90 self = SparcSystem()
91 if not mdesc:
92 # generic system
93 mdesc = SysConfig()
94 self.readfile = mdesc.script()
95 self.iobus = Bus(bus_id=0)
96 self.membus = MemBus(bus_id=1)
97 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
98 self.t1000 = T1000()
99 self.t1000.attachOnChipIO(self.membus)
100 self.t1000.attachIO(self.iobus)
101 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
102 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
103 self.bridge.side_a = self.iobus.port
104 self.bridge.side_b = self.membus.port
105 self.physmem.port = self.membus.port
106 self.physmem2.port = self.membus.port
107 self.rom.port = self.membus.port
108 self.nvram.port = self.membus.port
109 self.hypervisor_desc.port = self.membus.port
110 self.partition_desc.port = self.membus.port
111 self.intrctrl = IntrControl()
112 self.disk0 = CowMmDisk()
113 self.disk0.childImage(disk('disk.s10hw2'))
114 self.disk0.pio = self.iobus.port
115 self.reset_bin = binary('reset_new.bin')
116 self.hypervisor_bin = binary('q_new.bin')
117 self.openboot_bin = binary('openboot_new.bin')
118 self.nvram_bin = binary('nvram1')
119 self.hypervisor_desc_bin = binary('1up-hv.bin')
120 self.partition_desc_bin = binary('1up-md.bin')
121
122 return self
123
124def makeLinuxMipsSystem(mem_mode, mdesc = None):
125 class BaseMalta(Malta):
126 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
127 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
128 pci_func=0, pci_dev=0, pci_bus=0)
129
130 self = LinuxMipsSystem()
131 if not mdesc:
132 # generic system
133 mdesc = SysConfig()
134 self.readfile = mdesc.script()
135 self.iobus = Bus(bus_id=0)
136 self.membus = MemBus(bus_id=1)
137 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
138 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
139 self.bridge.side_a = self.iobus.port
140 self.bridge.side_b = self.membus.port
141 self.physmem.port = self.membus.port
142 self.disk0 = CowIdeDisk(driveID='master')
143 self.disk2 = CowIdeDisk(driveID='master')
144 self.disk0.childImage(mdesc.disk())
145 self.disk2.childImage(disk('linux-bigswap2.img'))
146 self.malta = BaseMalta()
147 self.malta.attachIO(self.iobus)
148 self.malta.ide.pio = self.iobus.port
149 self.malta.ethernet.pio = self.iobus.port
150 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
151 read_only = True))
152 self.intrctrl = IntrControl()
153 self.mem_mode = mem_mode
154 self.terminal = Terminal()
155 self.kernel = binary('mips/vmlinux')
156 self.console = binary('mips/console')
157 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
158
159 return self
160
161def x86IOAddress(port):
162 IO_address_space_base = 0x8000000000000000
163 return IO_address_space_base + port;
164
165def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
166 if self == None:
167 self = X86System()
168
169 if not mdesc:
170 # generic system
171 mdesc = SysConfig()
172 mdesc.diskname = 'x86root.img'
173 self.readfile = mdesc.script()
174
175 # Physical memory
176 self.membus = MemBus(bus_id=1)
177 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
178 self.physmem.port = self.membus.port
179
180 # North Bridge
181 self.iobus = Bus(bus_id=0)
182 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
183 self.bridge.side_a = self.iobus.port
184 self.bridge.side_b = self.membus.port
185
186 # Platform
187 self.pc = Pc()
188 self.pc.attachIO(self.iobus)
189
190 self.intrctrl = IntrControl()
191
192 # Disks
193 disk0 = CowIdeDisk(driveID='master')
194 disk2 = CowIdeDisk(driveID='master')
195 disk0.childImage(mdesc.disk())
196 disk2.childImage(disk('linux-bigswap2.img'))
197 self.pc.south_bridge.ide.disks = [disk0, disk2]
198
199 # Add in a Bios information structure.
200 structures = [X86SMBiosBiosInformation()]
201 self.smbios_table.structures = structures
202
203 # Set up the Intel MP table
204 for i in xrange(numCPUs):
205 bp = X86IntelMPProcessor(
206 local_apic_id = i,
207 local_apic_version = 0x14,
208 enable = True,
209 bootstrap = (i == 0))
210 self.intel_mp_table.add_entry(bp)
211 io_apic = X86IntelMPIOAPIC(
212 id = numCPUs,
213 version = 0x11,
214 enable = True,
215 address = 0xfec00000)
216 self.pc.south_bridge.io_apic.apic_id = io_apic.id
217 self.intel_mp_table.add_entry(io_apic)
218 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
219 self.intel_mp_table.add_entry(isa_bus)
220 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
221 self.intel_mp_table.add_entry(pci_bus)
222 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
223 subtractive_decode=True, parent_bus=1)
224 self.intel_mp_table.add_entry(connect_busses)
225 pci_dev4_inta = X86IntelMPIOIntAssignment(
226 interrupt_type = 'INT',
227 polarity = 'ConformPolarity',
228 trigger = 'ConformTrigger',
229 source_bus_id = 1,
230 source_bus_irq = 0 + (4 << 2),
231 dest_io_apic_id = io_apic.id,
232 dest_io_apic_intin = 16)
233 self.intel_mp_table.add_entry(pci_dev4_inta);
234 def assignISAInt(irq, apicPin):
235 assign_8259_to_apic = X86IntelMPIOIntAssignment(
236 interrupt_type = 'ExtInt',
237 polarity = 'ConformPolarity',
238 trigger = 'ConformTrigger',
239 source_bus_id = 0,
240 source_bus_irq = irq,
241 dest_io_apic_id = io_apic.id,
242 dest_io_apic_intin = 0)
243 self.intel_mp_table.add_entry(assign_8259_to_apic)
244 assign_to_apic = X86IntelMPIOIntAssignment(
245 interrupt_type = 'INT',
246 polarity = 'ConformPolarity',
247 trigger = 'ConformTrigger',
248 source_bus_id = 0,
249 source_bus_irq = irq,
250 dest_io_apic_id = io_apic.id,
251 dest_io_apic_intin = apicPin)
252 self.intel_mp_table.add_entry(assign_to_apic)
253 assignISAInt(0, 2)
254 assignISAInt(1, 1)
255 for i in range(3, 15):
256 assignISAInt(i, i)
257
258
259def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
260 self = LinuxX86System()
261
262 # Build up a generic x86 system and then specialize it for Linux
263 makeX86System(mem_mode, numCPUs, mdesc, self)
264
265 # We assume below that there's at least 1MB of memory. We'll require 2
266 # just to avoid corner cases.
267 assert(self.physmem.range.second >= 0x200000)
268
269 # Mark the first megabyte of memory as reserved
270 self.e820_table.entries.append(X86E820Entry(
271 addr = 0,
272 size = '1MB',
273 range_type = 2))
274
275 # Mark the rest as available
276 self.e820_table.entries.append(X86E820Entry(
277 addr = 0x100000,
278 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
279 range_type = 1))
280
281 # Command line
282 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
283 'root=/dev/hda1'
284 return self
285
286
287def makeDualRoot(testSystem, driveSystem, dumpfile):
288 self = Root()
289 self.testsys = testSystem
290 self.drivesys = driveSystem
291 self.etherlink = EtherLink()
292 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
293 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
294
295 if dumpfile:
296 self.etherdump = EtherDump(file=dumpfile)
297 self.etherlink.dump = Parent.etherdump
298
299 return self
300
301def setMipsOptions(TestCPUClass):
302 #CP0 Configuration
303 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
304 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
305 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
306 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
307
308 #CP0 Interrupt Control
309 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
310 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
311
312 # Config Register
313 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
314 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
315 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
316 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
317 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
318 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
319 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
320
321 #Config 1 Register
322 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
323 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
324 # ***VERY IMPORTANT***
325 # Remember to modify CP0_Config1 according to cache specs
326 # Examine file ../common/Cache.py
327 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
328 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
329 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
330 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
331 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
332 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
333 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
334 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
335 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
336 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
337 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
338 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
339 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
340
341 #Config 2 Register
342 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
343 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
344 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
345 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
346 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
347 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
348 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
349 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
350 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
351
352
353 #Config 3 Register
354 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
355 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
356 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
357 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
358 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
359 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
360 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
361 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
362 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
363
364 #SRS Ctl - HSS
365 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
366
367
368 #TestCPUClass.CoreParams.tlb = TLB()
369 #TestCPUClass.CoreParams.UnifiedTLB = 1
| 126def makeSparcSystem(mem_mode, mdesc = None):
127 class CowMmDisk(MmDisk):
128 image = CowDiskImage(child=RawDiskImage(read_only=True),
129 read_only=False)
130
131 def childImage(self, ci):
132 self.image.child.image_file = ci
133
134 self = SparcSystem()
135 if not mdesc:
136 # generic system
137 mdesc = SysConfig()
138 self.readfile = mdesc.script()
139 self.iobus = Bus(bus_id=0)
140 self.membus = MemBus(bus_id=1)
141 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
142 self.t1000 = T1000()
143 self.t1000.attachOnChipIO(self.membus)
144 self.t1000.attachIO(self.iobus)
145 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
146 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
147 self.bridge.side_a = self.iobus.port
148 self.bridge.side_b = self.membus.port
149 self.physmem.port = self.membus.port
150 self.physmem2.port = self.membus.port
151 self.rom.port = self.membus.port
152 self.nvram.port = self.membus.port
153 self.hypervisor_desc.port = self.membus.port
154 self.partition_desc.port = self.membus.port
155 self.intrctrl = IntrControl()
156 self.disk0 = CowMmDisk()
157 self.disk0.childImage(disk('disk.s10hw2'))
158 self.disk0.pio = self.iobus.port
159 self.reset_bin = binary('reset_new.bin')
160 self.hypervisor_bin = binary('q_new.bin')
161 self.openboot_bin = binary('openboot_new.bin')
162 self.nvram_bin = binary('nvram1')
163 self.hypervisor_desc_bin = binary('1up-hv.bin')
164 self.partition_desc_bin = binary('1up-md.bin')
165
166 return self
167
168def makeLinuxMipsSystem(mem_mode, mdesc = None):
169 class BaseMalta(Malta):
170 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
171 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
172 pci_func=0, pci_dev=0, pci_bus=0)
173
174 self = LinuxMipsSystem()
175 if not mdesc:
176 # generic system
177 mdesc = SysConfig()
178 self.readfile = mdesc.script()
179 self.iobus = Bus(bus_id=0)
180 self.membus = MemBus(bus_id=1)
181 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
182 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
183 self.bridge.side_a = self.iobus.port
184 self.bridge.side_b = self.membus.port
185 self.physmem.port = self.membus.port
186 self.disk0 = CowIdeDisk(driveID='master')
187 self.disk2 = CowIdeDisk(driveID='master')
188 self.disk0.childImage(mdesc.disk())
189 self.disk2.childImage(disk('linux-bigswap2.img'))
190 self.malta = BaseMalta()
191 self.malta.attachIO(self.iobus)
192 self.malta.ide.pio = self.iobus.port
193 self.malta.ethernet.pio = self.iobus.port
194 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
195 read_only = True))
196 self.intrctrl = IntrControl()
197 self.mem_mode = mem_mode
198 self.terminal = Terminal()
199 self.kernel = binary('mips/vmlinux')
200 self.console = binary('mips/console')
201 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
202
203 return self
204
205def x86IOAddress(port):
206 IO_address_space_base = 0x8000000000000000
207 return IO_address_space_base + port;
208
209def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
210 if self == None:
211 self = X86System()
212
213 if not mdesc:
214 # generic system
215 mdesc = SysConfig()
216 mdesc.diskname = 'x86root.img'
217 self.readfile = mdesc.script()
218
219 # Physical memory
220 self.membus = MemBus(bus_id=1)
221 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
222 self.physmem.port = self.membus.port
223
224 # North Bridge
225 self.iobus = Bus(bus_id=0)
226 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
227 self.bridge.side_a = self.iobus.port
228 self.bridge.side_b = self.membus.port
229
230 # Platform
231 self.pc = Pc()
232 self.pc.attachIO(self.iobus)
233
234 self.intrctrl = IntrControl()
235
236 # Disks
237 disk0 = CowIdeDisk(driveID='master')
238 disk2 = CowIdeDisk(driveID='master')
239 disk0.childImage(mdesc.disk())
240 disk2.childImage(disk('linux-bigswap2.img'))
241 self.pc.south_bridge.ide.disks = [disk0, disk2]
242
243 # Add in a Bios information structure.
244 structures = [X86SMBiosBiosInformation()]
245 self.smbios_table.structures = structures
246
247 # Set up the Intel MP table
248 for i in xrange(numCPUs):
249 bp = X86IntelMPProcessor(
250 local_apic_id = i,
251 local_apic_version = 0x14,
252 enable = True,
253 bootstrap = (i == 0))
254 self.intel_mp_table.add_entry(bp)
255 io_apic = X86IntelMPIOAPIC(
256 id = numCPUs,
257 version = 0x11,
258 enable = True,
259 address = 0xfec00000)
260 self.pc.south_bridge.io_apic.apic_id = io_apic.id
261 self.intel_mp_table.add_entry(io_apic)
262 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
263 self.intel_mp_table.add_entry(isa_bus)
264 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
265 self.intel_mp_table.add_entry(pci_bus)
266 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
267 subtractive_decode=True, parent_bus=1)
268 self.intel_mp_table.add_entry(connect_busses)
269 pci_dev4_inta = X86IntelMPIOIntAssignment(
270 interrupt_type = 'INT',
271 polarity = 'ConformPolarity',
272 trigger = 'ConformTrigger',
273 source_bus_id = 1,
274 source_bus_irq = 0 + (4 << 2),
275 dest_io_apic_id = io_apic.id,
276 dest_io_apic_intin = 16)
277 self.intel_mp_table.add_entry(pci_dev4_inta);
278 def assignISAInt(irq, apicPin):
279 assign_8259_to_apic = X86IntelMPIOIntAssignment(
280 interrupt_type = 'ExtInt',
281 polarity = 'ConformPolarity',
282 trigger = 'ConformTrigger',
283 source_bus_id = 0,
284 source_bus_irq = irq,
285 dest_io_apic_id = io_apic.id,
286 dest_io_apic_intin = 0)
287 self.intel_mp_table.add_entry(assign_8259_to_apic)
288 assign_to_apic = X86IntelMPIOIntAssignment(
289 interrupt_type = 'INT',
290 polarity = 'ConformPolarity',
291 trigger = 'ConformTrigger',
292 source_bus_id = 0,
293 source_bus_irq = irq,
294 dest_io_apic_id = io_apic.id,
295 dest_io_apic_intin = apicPin)
296 self.intel_mp_table.add_entry(assign_to_apic)
297 assignISAInt(0, 2)
298 assignISAInt(1, 1)
299 for i in range(3, 15):
300 assignISAInt(i, i)
301
302
303def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
304 self = LinuxX86System()
305
306 # Build up a generic x86 system and then specialize it for Linux
307 makeX86System(mem_mode, numCPUs, mdesc, self)
308
309 # We assume below that there's at least 1MB of memory. We'll require 2
310 # just to avoid corner cases.
311 assert(self.physmem.range.second >= 0x200000)
312
313 # Mark the first megabyte of memory as reserved
314 self.e820_table.entries.append(X86E820Entry(
315 addr = 0,
316 size = '1MB',
317 range_type = 2))
318
319 # Mark the rest as available
320 self.e820_table.entries.append(X86E820Entry(
321 addr = 0x100000,
322 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
323 range_type = 1))
324
325 # Command line
326 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
327 'root=/dev/hda1'
328 return self
329
330
331def makeDualRoot(testSystem, driveSystem, dumpfile):
332 self = Root()
333 self.testsys = testSystem
334 self.drivesys = driveSystem
335 self.etherlink = EtherLink()
336 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
337 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
338
339 if dumpfile:
340 self.etherdump = EtherDump(file=dumpfile)
341 self.etherlink.dump = Parent.etherdump
342
343 return self
344
345def setMipsOptions(TestCPUClass):
346 #CP0 Configuration
347 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
348 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
349 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
350 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
351
352 #CP0 Interrupt Control
353 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
354 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
355
356 # Config Register
357 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
358 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
359 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
360 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
361 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
362 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
363 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
364
365 #Config 1 Register
366 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
367 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
368 # ***VERY IMPORTANT***
369 # Remember to modify CP0_Config1 according to cache specs
370 # Examine file ../common/Cache.py
371 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
372 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
373 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
374 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
375 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
376 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
377 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
378 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
379 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
380 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
381 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
382 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
383 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
384
385 #Config 2 Register
386 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
387 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
388 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
389 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
390 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
391 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
392 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
393 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
394 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
395
396
397 #Config 3 Register
398 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
399 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
400 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
401 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
402 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
403 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
404 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
405 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
406 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
407
408 #SRS Ctl - HSS
409 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
410
411
412 #TestCPUClass.CoreParams.tlb = TLB()
413 #TestCPUClass.CoreParams.UnifiedTLB = 1
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