1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29import m5
30from m5 import makeList
31from m5.objects import *
32from Benchmarks import *
33
34class CowIdeDisk(IdeDisk):
35 image = CowDiskImage(child=RawDiskImage(read_only=True),
36 read_only=False)
37
38 def childImage(self, ci):
39 self.image.child.image_file = ci
40
41def makeLinuxAlphaSystem(mem_mode, mdesc = None):
42 class BaseTsunami(Tsunami):
43 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
44 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
45 pci_func=0, pci_dev=0, pci_bus=0)
46
47 self = LinuxAlphaSystem()
48 if not mdesc:
49 # generic system
50 mdesc = SysConfig()
51 self.readfile = mdesc.script()
52 self.iobus = Bus(bus_id=0)
53 self.membus = Bus(bus_id=1)
54 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
55 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
56 self.bridge.side_a = self.iobus.port
57 self.bridge.side_b = self.membus.port
58 self.physmem.port = self.membus.port
59 self.disk0 = CowIdeDisk(driveID='master')
60 self.disk2 = CowIdeDisk(driveID='master')
61 self.disk0.childImage(mdesc.disk())
62 self.disk2.childImage(disk('linux-bigswap2.img'))
63 self.tsunami = BaseTsunami()
64 self.tsunami.attachIO(self.iobus)
65 self.tsunami.ide.pio = self.iobus.port
66 self.tsunami.ethernet.pio = self.iobus.port
67 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
68 read_only = True))
69 self.intrctrl = IntrControl()
70 self.mem_mode = mem_mode
71 self.terminal = Terminal()
72 self.kernel = binary('vmlinux')
73 self.pal = binary('ts_osfpal')
74 self.console = binary('console')
75 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
76
77 return self
78
79def makeSparcSystem(mem_mode, mdesc = None):
80 class CowMmDisk(MmDisk):
81 image = CowDiskImage(child=RawDiskImage(read_only=True),
82 read_only=False)
83
84 def childImage(self, ci):
85 self.image.child.image_file = ci
86
87 self = SparcSystem()
88 if not mdesc:
89 # generic system
90 mdesc = SysConfig()
91 self.readfile = mdesc.script()
92 self.iobus = Bus(bus_id=0)
93 self.membus = Bus(bus_id=1)
94 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
95 self.t1000 = T1000()
96 self.t1000.attachOnChipIO(self.membus)
97 self.t1000.attachIO(self.iobus)
98 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
99 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
100 self.bridge.side_a = self.iobus.port
101 self.bridge.side_b = self.membus.port
102 self.physmem.port = self.membus.port
103 self.physmem2.port = self.membus.port
104 self.rom.port = self.membus.port
105 self.nvram.port = self.membus.port
106 self.hypervisor_desc.port = self.membus.port
107 self.partition_desc.port = self.membus.port
108 self.intrctrl = IntrControl()
109 self.disk0 = CowMmDisk()
110 self.disk0.childImage(disk('disk.s10hw2'))
111 self.disk0.pio = self.iobus.port
112 self.reset_bin = binary('reset_new.bin')
113 self.hypervisor_bin = binary('q_new.bin')
114 self.openboot_bin = binary('openboot_new.bin')
115 self.nvram_bin = binary('nvram1')
116 self.hypervisor_desc_bin = binary('1up-hv.bin')
117 self.partition_desc_bin = binary('1up-md.bin')
118
119 return self
120
121def makeLinuxMipsSystem(mem_mode, mdesc = None):
122 class BaseMalta(Malta):
123 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
124 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
125 pci_func=0, pci_dev=0, pci_bus=0)
126
127 self = LinuxMipsSystem()
128 if not mdesc:
129 # generic system
130 mdesc = SysConfig()
131 self.readfile = mdesc.script()
132 self.iobus = Bus(bus_id=0)
133 self.membus = Bus(bus_id=1)
134 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
135 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
136 self.bridge.side_a = self.iobus.port
137 self.bridge.side_b = self.membus.port
138 self.physmem.port = self.membus.port
139 self.disk0 = CowIdeDisk(driveID='master')
140 self.disk2 = CowIdeDisk(driveID='master')
141 self.disk0.childImage(mdesc.disk())
142 self.disk2.childImage(disk('linux-bigswap2.img'))
143 self.malta = BaseMalta()
144 self.malta.attachIO(self.iobus)
145 self.malta.ide.pio = self.iobus.port
146 self.malta.ethernet.pio = self.iobus.port
147 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
148 read_only = True))
149 self.intrctrl = IntrControl()
150 self.mem_mode = mem_mode
151 self.terminal = Terminal()
152 self.kernel = binary('mips/vmlinux')
153 self.console = binary('mips/console')
154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
155
156 return self
157
158def x86IOAddress(port):
159 IO_address_space_base = 0x8000000000000000
160 return IO_address_space_base + port;
161
162def makeX86System(mem_mode, mdesc = None, self = None):
163 if self == None:
164 self = X86System()
165
166 if not mdesc:
167 # generic system
168 mdesc = SysConfig()
| 1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29import m5
30from m5 import makeList
31from m5.objects import *
32from Benchmarks import *
33
34class CowIdeDisk(IdeDisk):
35 image = CowDiskImage(child=RawDiskImage(read_only=True),
36 read_only=False)
37
38 def childImage(self, ci):
39 self.image.child.image_file = ci
40
41def makeLinuxAlphaSystem(mem_mode, mdesc = None):
42 class BaseTsunami(Tsunami):
43 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
44 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
45 pci_func=0, pci_dev=0, pci_bus=0)
46
47 self = LinuxAlphaSystem()
48 if not mdesc:
49 # generic system
50 mdesc = SysConfig()
51 self.readfile = mdesc.script()
52 self.iobus = Bus(bus_id=0)
53 self.membus = Bus(bus_id=1)
54 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
55 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
56 self.bridge.side_a = self.iobus.port
57 self.bridge.side_b = self.membus.port
58 self.physmem.port = self.membus.port
59 self.disk0 = CowIdeDisk(driveID='master')
60 self.disk2 = CowIdeDisk(driveID='master')
61 self.disk0.childImage(mdesc.disk())
62 self.disk2.childImage(disk('linux-bigswap2.img'))
63 self.tsunami = BaseTsunami()
64 self.tsunami.attachIO(self.iobus)
65 self.tsunami.ide.pio = self.iobus.port
66 self.tsunami.ethernet.pio = self.iobus.port
67 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
68 read_only = True))
69 self.intrctrl = IntrControl()
70 self.mem_mode = mem_mode
71 self.terminal = Terminal()
72 self.kernel = binary('vmlinux')
73 self.pal = binary('ts_osfpal')
74 self.console = binary('console')
75 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
76
77 return self
78
79def makeSparcSystem(mem_mode, mdesc = None):
80 class CowMmDisk(MmDisk):
81 image = CowDiskImage(child=RawDiskImage(read_only=True),
82 read_only=False)
83
84 def childImage(self, ci):
85 self.image.child.image_file = ci
86
87 self = SparcSystem()
88 if not mdesc:
89 # generic system
90 mdesc = SysConfig()
91 self.readfile = mdesc.script()
92 self.iobus = Bus(bus_id=0)
93 self.membus = Bus(bus_id=1)
94 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
95 self.t1000 = T1000()
96 self.t1000.attachOnChipIO(self.membus)
97 self.t1000.attachIO(self.iobus)
98 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
99 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
100 self.bridge.side_a = self.iobus.port
101 self.bridge.side_b = self.membus.port
102 self.physmem.port = self.membus.port
103 self.physmem2.port = self.membus.port
104 self.rom.port = self.membus.port
105 self.nvram.port = self.membus.port
106 self.hypervisor_desc.port = self.membus.port
107 self.partition_desc.port = self.membus.port
108 self.intrctrl = IntrControl()
109 self.disk0 = CowMmDisk()
110 self.disk0.childImage(disk('disk.s10hw2'))
111 self.disk0.pio = self.iobus.port
112 self.reset_bin = binary('reset_new.bin')
113 self.hypervisor_bin = binary('q_new.bin')
114 self.openboot_bin = binary('openboot_new.bin')
115 self.nvram_bin = binary('nvram1')
116 self.hypervisor_desc_bin = binary('1up-hv.bin')
117 self.partition_desc_bin = binary('1up-md.bin')
118
119 return self
120
121def makeLinuxMipsSystem(mem_mode, mdesc = None):
122 class BaseMalta(Malta):
123 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
124 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
125 pci_func=0, pci_dev=0, pci_bus=0)
126
127 self = LinuxMipsSystem()
128 if not mdesc:
129 # generic system
130 mdesc = SysConfig()
131 self.readfile = mdesc.script()
132 self.iobus = Bus(bus_id=0)
133 self.membus = Bus(bus_id=1)
134 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
135 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
136 self.bridge.side_a = self.iobus.port
137 self.bridge.side_b = self.membus.port
138 self.physmem.port = self.membus.port
139 self.disk0 = CowIdeDisk(driveID='master')
140 self.disk2 = CowIdeDisk(driveID='master')
141 self.disk0.childImage(mdesc.disk())
142 self.disk2.childImage(disk('linux-bigswap2.img'))
143 self.malta = BaseMalta()
144 self.malta.attachIO(self.iobus)
145 self.malta.ide.pio = self.iobus.port
146 self.malta.ethernet.pio = self.iobus.port
147 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
148 read_only = True))
149 self.intrctrl = IntrControl()
150 self.mem_mode = mem_mode
151 self.terminal = Terminal()
152 self.kernel = binary('mips/vmlinux')
153 self.console = binary('mips/console')
154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
155
156 return self
157
158def x86IOAddress(port):
159 IO_address_space_base = 0x8000000000000000
160 return IO_address_space_base + port;
161
162def makeX86System(mem_mode, mdesc = None, self = None):
163 if self == None:
164 self = X86System()
165
166 if not mdesc:
167 # generic system
168 mdesc = SysConfig()
|
188 # Add in a Bios information structure.
189 structures = [X86SMBiosBiosInformation()]
190 self.smbios_table.structures = structures
191
192 # Set up the Intel MP table
193 bp = X86IntelMPProcessor(
194 local_apic_id = 0,
195 local_apic_version = 0x14,
196 enable = True,
197 bootstrap = True)
198 self.intel_mp_table.add_entry(bp)
199 io_apic = X86IntelMPIOAPIC(
200 id = 1,
201 version = 0x11,
202 enable = True,
203 address = 0xfec00000)
204 self.intel_mp_table.add_entry(io_apic)
205 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
206 self.intel_mp_table.add_entry(isa_bus)
207 assign_8259_0_to_apic = X86IntelMPIOIntAssignment(
208 interrupt_type = 'ExtInt',
209 polarity = 'ConformPolarity',
210 trigger = 'ConformTrigger',
211 source_bus_id = 0,
212 source_bus_irq = 0,
213 dest_io_apic_id = 1,
214 dest_io_apic_intin = 0)
215 self.intel_mp_table.add_entry(assign_8259_0_to_apic)
216 assign_0_to_apic = X86IntelMPIOIntAssignment(
217 interrupt_type = 'INT',
218 polarity = 'ConformPolarity',
219 trigger = 'ConformTrigger',
220 source_bus_id = 0,
221 source_bus_irq = 0,
222 dest_io_apic_id = 1,
223 dest_io_apic_intin = 2)
224 self.intel_mp_table.add_entry(assign_0_to_apic)
225 assign_8259_1_to_apic = X86IntelMPIOIntAssignment(
226 interrupt_type = 'ExtInt',
227 polarity = 'ConformPolarity',
228 trigger = 'ConformTrigger',
229 source_bus_id = 0,
230 source_bus_irq = 1,
231 dest_io_apic_id = 1,
232 dest_io_apic_intin = 0)
233 self.intel_mp_table.add_entry(assign_8259_1_to_apic)
234 assign_1_to_apic = X86IntelMPIOIntAssignment(
235 interrupt_type = 'INT',
236 polarity = 'ConformPolarity',
237 trigger = 'ConformTrigger',
238 source_bus_id = 0,
239 source_bus_irq = 1,
240 dest_io_apic_id = 1,
241 dest_io_apic_intin = 1)
242 self.intel_mp_table.add_entry(assign_1_to_apic)
243 assign_8259_12_to_apic = X86IntelMPIOIntAssignment(
244 interrupt_type = 'ExtInt',
245 polarity = 'ConformPolarity',
246 trigger = 'ConformTrigger',
247 source_bus_id = 0,
248 source_bus_irq = 12,
249 dest_io_apic_id = 1,
250 dest_io_apic_intin = 0)
251 self.intel_mp_table.add_entry(assign_8259_12_to_apic)
252 assign_12_to_apic = X86IntelMPIOIntAssignment(
253 interrupt_type = 'INT',
254 polarity = 'ConformPolarity',
255 trigger = 'ConformTrigger',
256 source_bus_id = 0,
257 source_bus_irq = 12,
258 dest_io_apic_id = 1,
259 dest_io_apic_intin = 12)
260 self.intel_mp_table.add_entry(assign_12_to_apic)
261
262
263def makeLinuxX86System(mem_mode, mdesc = None):
264 self = LinuxX86System()
265
266 # Build up a generic x86 system and then specialize it for Linux
267 makeX86System(mem_mode, mdesc, self)
268
269 # We assume below that there's at least 1MB of memory. We'll require 2
270 # just to avoid corner cases.
271 assert(self.physmem.range.second >= 0x200000)
272
273 # Mark the first megabyte of memory as reserved
274 self.e820_table.entries.append(X86E820Entry(
275 addr = 0,
276 size = '1MB',
277 range_type = 2))
278
279 # Mark the rest as available
280 self.e820_table.entries.append(X86E820Entry(
281 addr = 0x100000,
282 size = '%dB' % (self.physmem.range.second - 0x100000 - 1),
283 range_type = 1))
284
285 # Command line
286 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=9608015'
287 return self
288
289
290def makeDualRoot(testSystem, driveSystem, dumpfile):
291 self = Root()
292 self.testsys = testSystem
293 self.drivesys = driveSystem
294 self.etherlink = EtherLink()
295 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
296 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
297
298 if dumpfile:
299 self.etherdump = EtherDump(file=dumpfile)
300 self.etherlink.dump = Parent.etherdump
301
302 return self
303
304def setMipsOptions(TestCPUClass):
305 #CP0 Configuration
306 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
307 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
308 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
309 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
310
311 #CP0 Interrupt Control
312 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
313 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
314
315 # Config Register
316 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
317 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
318 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
319 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
320 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
321 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
322 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
323
324 #Config 1 Register
325 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
326 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
327 # ***VERY IMPORTANT***
328 # Remember to modify CP0_Config1 according to cache specs
329 # Examine file ../common/Cache.py
330 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
331 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
332 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
333 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
334 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
335 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
336 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
337 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
338 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
339 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
340 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
341 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
342 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
343
344 #Config 2 Register
345 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
346 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
347 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
348 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
349 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
350 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
351 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
352 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
353 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
354
355
356 #Config 3 Register
357 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
358 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
359 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
360 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
361 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
362 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
363 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
364 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
365 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
366
367 #SRS Ctl - HSS
368 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
369
370
371 #TestCPUClass.CoreParams.tlb = TLB()
372 #TestCPUClass.CoreParams.UnifiedTLB = 1
| 196 # Add in a Bios information structure.
197 structures = [X86SMBiosBiosInformation()]
198 self.smbios_table.structures = structures
199
200 # Set up the Intel MP table
201 bp = X86IntelMPProcessor(
202 local_apic_id = 0,
203 local_apic_version = 0x14,
204 enable = True,
205 bootstrap = True)
206 self.intel_mp_table.add_entry(bp)
207 io_apic = X86IntelMPIOAPIC(
208 id = 1,
209 version = 0x11,
210 enable = True,
211 address = 0xfec00000)
212 self.intel_mp_table.add_entry(io_apic)
213 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
214 self.intel_mp_table.add_entry(isa_bus)
215 assign_8259_0_to_apic = X86IntelMPIOIntAssignment(
216 interrupt_type = 'ExtInt',
217 polarity = 'ConformPolarity',
218 trigger = 'ConformTrigger',
219 source_bus_id = 0,
220 source_bus_irq = 0,
221 dest_io_apic_id = 1,
222 dest_io_apic_intin = 0)
223 self.intel_mp_table.add_entry(assign_8259_0_to_apic)
224 assign_0_to_apic = X86IntelMPIOIntAssignment(
225 interrupt_type = 'INT',
226 polarity = 'ConformPolarity',
227 trigger = 'ConformTrigger',
228 source_bus_id = 0,
229 source_bus_irq = 0,
230 dest_io_apic_id = 1,
231 dest_io_apic_intin = 2)
232 self.intel_mp_table.add_entry(assign_0_to_apic)
233 assign_8259_1_to_apic = X86IntelMPIOIntAssignment(
234 interrupt_type = 'ExtInt',
235 polarity = 'ConformPolarity',
236 trigger = 'ConformTrigger',
237 source_bus_id = 0,
238 source_bus_irq = 1,
239 dest_io_apic_id = 1,
240 dest_io_apic_intin = 0)
241 self.intel_mp_table.add_entry(assign_8259_1_to_apic)
242 assign_1_to_apic = X86IntelMPIOIntAssignment(
243 interrupt_type = 'INT',
244 polarity = 'ConformPolarity',
245 trigger = 'ConformTrigger',
246 source_bus_id = 0,
247 source_bus_irq = 1,
248 dest_io_apic_id = 1,
249 dest_io_apic_intin = 1)
250 self.intel_mp_table.add_entry(assign_1_to_apic)
251 assign_8259_12_to_apic = X86IntelMPIOIntAssignment(
252 interrupt_type = 'ExtInt',
253 polarity = 'ConformPolarity',
254 trigger = 'ConformTrigger',
255 source_bus_id = 0,
256 source_bus_irq = 12,
257 dest_io_apic_id = 1,
258 dest_io_apic_intin = 0)
259 self.intel_mp_table.add_entry(assign_8259_12_to_apic)
260 assign_12_to_apic = X86IntelMPIOIntAssignment(
261 interrupt_type = 'INT',
262 polarity = 'ConformPolarity',
263 trigger = 'ConformTrigger',
264 source_bus_id = 0,
265 source_bus_irq = 12,
266 dest_io_apic_id = 1,
267 dest_io_apic_intin = 12)
268 self.intel_mp_table.add_entry(assign_12_to_apic)
269
270
271def makeLinuxX86System(mem_mode, mdesc = None):
272 self = LinuxX86System()
273
274 # Build up a generic x86 system and then specialize it for Linux
275 makeX86System(mem_mode, mdesc, self)
276
277 # We assume below that there's at least 1MB of memory. We'll require 2
278 # just to avoid corner cases.
279 assert(self.physmem.range.second >= 0x200000)
280
281 # Mark the first megabyte of memory as reserved
282 self.e820_table.entries.append(X86E820Entry(
283 addr = 0,
284 size = '1MB',
285 range_type = 2))
286
287 # Mark the rest as available
288 self.e820_table.entries.append(X86E820Entry(
289 addr = 0x100000,
290 size = '%dB' % (self.physmem.range.second - 0x100000 - 1),
291 range_type = 1))
292
293 # Command line
294 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=9608015'
295 return self
296
297
298def makeDualRoot(testSystem, driveSystem, dumpfile):
299 self = Root()
300 self.testsys = testSystem
301 self.drivesys = driveSystem
302 self.etherlink = EtherLink()
303 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
304 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
305
306 if dumpfile:
307 self.etherdump = EtherDump(file=dumpfile)
308 self.etherlink.dump = Parent.etherdump
309
310 return self
311
312def setMipsOptions(TestCPUClass):
313 #CP0 Configuration
314 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
315 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
316 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
317 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
318
319 #CP0 Interrupt Control
320 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
321 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
322
323 # Config Register
324 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
325 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
326 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
327 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
328 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
329 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
330 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
331
332 #Config 1 Register
333 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
334 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
335 # ***VERY IMPORTANT***
336 # Remember to modify CP0_Config1 according to cache specs
337 # Examine file ../common/Cache.py
338 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
339 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
340 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
341 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
342 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
343 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
344 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
345 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
346 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
347 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
348 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
349 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
350 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
351
352 #Config 2 Register
353 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
354 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
355 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
356 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
357 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
358 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
359 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
360 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
361 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
362
363
364 #Config 3 Register
365 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
366 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
367 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
368 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
369 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
370 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
371 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
372 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
373 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
374
375 #SRS Ctl - HSS
376 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
377
378
379 #TestCPUClass.CoreParams.tlb = TLB()
380 #TestCPUClass.CoreParams.UnifiedTLB = 1
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