1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29import m5
30from m5 import makeList
31from m5.objects import *
32from Benchmarks import *
33
34class CowIdeDisk(IdeDisk):
35 image = CowDiskImage(child=RawDiskImage(read_only=True),
36 read_only=False)
37
38 def childImage(self, ci):
39 self.image.child.image_file = ci
40
41def makeLinuxAlphaSystem(mem_mode, mdesc = None):
42 class BaseTsunami(Tsunami):
43 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
44 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
45 pci_func=0, pci_dev=0, pci_bus=0)
46
47 self = LinuxAlphaSystem()
48 if not mdesc:
49 # generic system
50 mdesc = SysConfig()
51 self.readfile = mdesc.script()
52 self.iobus = Bus(bus_id=0)
53 self.membus = Bus(bus_id=1)
54 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
55 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
56 self.bridge.side_a = self.iobus.port
57 self.bridge.side_b = self.membus.port
58 self.physmem.port = self.membus.port
59 self.disk0 = CowIdeDisk(driveID='master')
60 self.disk2 = CowIdeDisk(driveID='master')
61 self.disk0.childImage(mdesc.disk())
62 self.disk2.childImage(disk('linux-bigswap2.img'))
63 self.tsunami = BaseTsunami()
64 self.tsunami.attachIO(self.iobus)
65 self.tsunami.ide.pio = self.iobus.port
66 self.tsunami.ethernet.pio = self.iobus.port
67 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
68 read_only = True))
69 self.intrctrl = IntrControl()
70 self.mem_mode = mem_mode
71 self.sim_console = SimConsole()
72 self.kernel = binary('vmlinux')
73 self.pal = binary('ts_osfpal')
74 self.console = binary('console')
75 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
76
77 return self
78
79def makeSparcSystem(mem_mode, mdesc = None):
80 class CowMmDisk(MmDisk):
81 image = CowDiskImage(child=RawDiskImage(read_only=True),
82 read_only=False)
83
84 def childImage(self, ci):
85 self.image.child.image_file = ci
86
87 self = SparcSystem()
88 if not mdesc:
89 # generic system
90 mdesc = SysConfig()
91 self.readfile = mdesc.script()
92 self.iobus = Bus(bus_id=0)
93 self.membus = Bus(bus_id=1)
94 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
95 self.t1000 = T1000()
96 self.t1000.attachOnChipIO(self.membus)
97 self.t1000.attachIO(self.iobus)
98 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
99 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
100 self.bridge.side_a = self.iobus.port
101 self.bridge.side_b = self.membus.port
102 self.physmem.port = self.membus.port
103 self.physmem2.port = self.membus.port
104 self.rom.port = self.membus.port
105 self.nvram.port = self.membus.port
106 self.hypervisor_desc.port = self.membus.port
107 self.partition_desc.port = self.membus.port
108 self.intrctrl = IntrControl()
109 self.disk0 = CowMmDisk()
110 self.disk0.childImage(disk('disk.s10hw2'))
111 self.disk0.pio = self.iobus.port
112 self.reset_bin = binary('reset_new.bin')
113 self.hypervisor_bin = binary('q_new.bin')
114 self.openboot_bin = binary('openboot_new.bin')
115 self.nvram_bin = binary('nvram1')
116 self.hypervisor_desc_bin = binary('1up-hv.bin')
117 self.partition_desc_bin = binary('1up-md.bin')
118
119 return self
120
121def makeLinuxMipsSystem(mem_mode, mdesc = None):
122 class BaseMalta(Malta):
123 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
124 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
125 pci_func=0, pci_dev=0, pci_bus=0)
126
127 self = LinuxMipsSystem()
128 if not mdesc:
129 # generic system
130 mdesc = SysConfig()
131 self.readfile = mdesc.script()
132 self.iobus = Bus(bus_id=0)
133 self.membus = Bus(bus_id=1)
134 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
135 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
136 self.bridge.side_a = self.iobus.port
137 self.bridge.side_b = self.membus.port
138 self.physmem.port = self.membus.port
139 self.disk0 = CowIdeDisk(driveID='master')
140 self.disk2 = CowIdeDisk(driveID='master')
141 self.disk0.childImage(mdesc.disk())
142 self.disk2.childImage(disk('linux-bigswap2.img'))
143 self.malta = BaseMalta()
144 self.malta.attachIO(self.iobus)
145 self.malta.ide.pio = self.iobus.port
146 self.malta.ethernet.pio = self.iobus.port
147 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
148 read_only = True))
149 self.intrctrl = IntrControl()
150 self.mem_mode = mem_mode
151 self.sim_console = SimConsole()
152 self.kernel = binary('mips/vmlinux')
153 self.console = binary('mips/console')
154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
155
156 return self
157
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29import m5
30from m5 import makeList
31from m5.objects import *
32from Benchmarks import *
33
34class CowIdeDisk(IdeDisk):
35 image = CowDiskImage(child=RawDiskImage(read_only=True),
36 read_only=False)
37
38 def childImage(self, ci):
39 self.image.child.image_file = ci
40
41def makeLinuxAlphaSystem(mem_mode, mdesc = None):
42 class BaseTsunami(Tsunami):
43 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
44 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
45 pci_func=0, pci_dev=0, pci_bus=0)
46
47 self = LinuxAlphaSystem()
48 if not mdesc:
49 # generic system
50 mdesc = SysConfig()
51 self.readfile = mdesc.script()
52 self.iobus = Bus(bus_id=0)
53 self.membus = Bus(bus_id=1)
54 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
55 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
56 self.bridge.side_a = self.iobus.port
57 self.bridge.side_b = self.membus.port
58 self.physmem.port = self.membus.port
59 self.disk0 = CowIdeDisk(driveID='master')
60 self.disk2 = CowIdeDisk(driveID='master')
61 self.disk0.childImage(mdesc.disk())
62 self.disk2.childImage(disk('linux-bigswap2.img'))
63 self.tsunami = BaseTsunami()
64 self.tsunami.attachIO(self.iobus)
65 self.tsunami.ide.pio = self.iobus.port
66 self.tsunami.ethernet.pio = self.iobus.port
67 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
68 read_only = True))
69 self.intrctrl = IntrControl()
70 self.mem_mode = mem_mode
71 self.sim_console = SimConsole()
72 self.kernel = binary('vmlinux')
73 self.pal = binary('ts_osfpal')
74 self.console = binary('console')
75 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
76
77 return self
78
79def makeSparcSystem(mem_mode, mdesc = None):
80 class CowMmDisk(MmDisk):
81 image = CowDiskImage(child=RawDiskImage(read_only=True),
82 read_only=False)
83
84 def childImage(self, ci):
85 self.image.child.image_file = ci
86
87 self = SparcSystem()
88 if not mdesc:
89 # generic system
90 mdesc = SysConfig()
91 self.readfile = mdesc.script()
92 self.iobus = Bus(bus_id=0)
93 self.membus = Bus(bus_id=1)
94 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
95 self.t1000 = T1000()
96 self.t1000.attachOnChipIO(self.membus)
97 self.t1000.attachIO(self.iobus)
98 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
99 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
100 self.bridge.side_a = self.iobus.port
101 self.bridge.side_b = self.membus.port
102 self.physmem.port = self.membus.port
103 self.physmem2.port = self.membus.port
104 self.rom.port = self.membus.port
105 self.nvram.port = self.membus.port
106 self.hypervisor_desc.port = self.membus.port
107 self.partition_desc.port = self.membus.port
108 self.intrctrl = IntrControl()
109 self.disk0 = CowMmDisk()
110 self.disk0.childImage(disk('disk.s10hw2'))
111 self.disk0.pio = self.iobus.port
112 self.reset_bin = binary('reset_new.bin')
113 self.hypervisor_bin = binary('q_new.bin')
114 self.openboot_bin = binary('openboot_new.bin')
115 self.nvram_bin = binary('nvram1')
116 self.hypervisor_desc_bin = binary('1up-hv.bin')
117 self.partition_desc_bin = binary('1up-md.bin')
118
119 return self
120
121def makeLinuxMipsSystem(mem_mode, mdesc = None):
122 class BaseMalta(Malta):
123 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
124 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
125 pci_func=0, pci_dev=0, pci_bus=0)
126
127 self = LinuxMipsSystem()
128 if not mdesc:
129 # generic system
130 mdesc = SysConfig()
131 self.readfile = mdesc.script()
132 self.iobus = Bus(bus_id=0)
133 self.membus = Bus(bus_id=1)
134 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
135 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
136 self.bridge.side_a = self.iobus.port
137 self.bridge.side_b = self.membus.port
138 self.physmem.port = self.membus.port
139 self.disk0 = CowIdeDisk(driveID='master')
140 self.disk2 = CowIdeDisk(driveID='master')
141 self.disk0.childImage(mdesc.disk())
142 self.disk2.childImage(disk('linux-bigswap2.img'))
143 self.malta = BaseMalta()
144 self.malta.attachIO(self.iobus)
145 self.malta.ide.pio = self.iobus.port
146 self.malta.ethernet.pio = self.iobus.port
147 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
148 read_only = True))
149 self.intrctrl = IntrControl()
150 self.mem_mode = mem_mode
151 self.sim_console = SimConsole()
152 self.kernel = binary('mips/vmlinux')
153 self.console = binary('mips/console')
154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
155
156 return self
157
|
160 if not mdesc:
161 # generic system
162 mdesc = SysConfig()
163 self.readfile = mdesc.script()
164
165 # Physical memory
166 self.membus = Bus(bus_id=0)
167 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
168 self.physmem.port = self.membus.port
169
170 # Platform
171 self.opteron = Opteron()
172
173 self.intrctrl = IntrControl()
174
175 return self
176
177
178def makeDualRoot(testSystem, driveSystem, dumpfile):
179 self = Root()
180 self.testsys = testSystem
181 self.drivesys = driveSystem
182 self.etherlink = EtherLink()
183 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
184 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
185
186 if dumpfile:
187 self.etherdump = EtherDump(file=dumpfile)
188 self.etherlink.dump = Parent.etherdump
189
190 return self
191
192def setMipsOptions(TestCPUClass):
193 #CP0 Configuration
194 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
195 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
196 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
197 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
198
199 #CP0 Interrupt Control
200 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
201 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
202
203 # Config Register
204 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
205 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
206 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
207 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
208 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
209 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
210 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
211
212 #Config 1 Register
213 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
214 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
215 # ***VERY IMPORTANT***
216 # Remember to modify CP0_Config1 according to cache specs
217 # Examine file ../common/Cache.py
218 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
219 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
220 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
221 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
222 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
223 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
224 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
225 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
226 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
227 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
228 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
229 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
230 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
231
232 #Config 2 Register
233 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
234 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
235 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
236 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
237 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
238 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
239 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
240 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
241 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
242
243
244 #Config 3 Register
245 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
246 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
247 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
248 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
249 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
250 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
251 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
252 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
253 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
254
255 #SRS Ctl - HSS
256 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
257
258
259 #TestCPUClass.CoreParams.tlb = TLB()
260 #TestCPUClass.CoreParams.UnifiedTLB = 1
| 160 if not mdesc:
161 # generic system
162 mdesc = SysConfig()
163 self.readfile = mdesc.script()
164
165 # Physical memory
166 self.membus = Bus(bus_id=0)
167 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
168 self.physmem.port = self.membus.port
169
170 # Platform
171 self.opteron = Opteron()
172
173 self.intrctrl = IntrControl()
174
175 return self
176
177
178def makeDualRoot(testSystem, driveSystem, dumpfile):
179 self = Root()
180 self.testsys = testSystem
181 self.drivesys = driveSystem
182 self.etherlink = EtherLink()
183 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
184 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
185
186 if dumpfile:
187 self.etherdump = EtherDump(file=dumpfile)
188 self.etherlink.dump = Parent.etherdump
189
190 return self
191
192def setMipsOptions(TestCPUClass):
193 #CP0 Configuration
194 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
195 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
196 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
197 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
198
199 #CP0 Interrupt Control
200 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
201 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
202
203 # Config Register
204 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
205 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
206 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
207 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
208 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
209 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
210 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
211
212 #Config 1 Register
213 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
214 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
215 # ***VERY IMPORTANT***
216 # Remember to modify CP0_Config1 according to cache specs
217 # Examine file ../common/Cache.py
218 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
219 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
220 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
221 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
222 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
223 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
224 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
225 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
226 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
227 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
228 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
229 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
230 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
231
232 #Config 2 Register
233 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
234 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
235 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
236 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
237 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
238 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
239 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
240 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
241 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
242
243
244 #Config 3 Register
245 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
246 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
247 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
248 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
249 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
250 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
251 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
252 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
253 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
254
255 #SRS Ctl - HSS
256 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
257
258
259 #TestCPUClass.CoreParams.tlb = TLB()
260 #TestCPUClass.CoreParams.UnifiedTLB = 1
|