1# Copyright (c) 2010-2012, 2015-2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from __future__ import print_function
43
44from m5.objects import *
45from Benchmarks import *
46from m5.util import *
47from common import PlatformConfig
48
49# Populate to reflect supported os types per target ISA
50os_types = { 'alpha' : [ 'linux' ],
51 'mips' : [ 'linux' ],
52 'sparc' : [ 'linux' ],
53 'x86' : [ 'linux' ],
54 'arm' : [ 'linux',
55 'android-gingerbread',
56 'android-ics',
57 'android-jellybean',
58 'android-kitkat',
59 'android-nougat', ],
60 }
61
62class CowIdeDisk(IdeDisk):
63 image = CowDiskImage(child=RawDiskImage(read_only=True),
64 read_only=False)
65
66 def childImage(self, ci):
67 self.image.child.image_file = ci
68
69class MemBus(SystemXBar):
70 badaddr_responder = BadAddr()
71 default = Self.badaddr_responder.pio
72
73def fillInCmdline(mdesc, template, **kwargs):
74 kwargs.setdefault('disk', mdesc.disk())
75 kwargs.setdefault('rootdev', mdesc.rootdev())
76 kwargs.setdefault('mem', mdesc.mem())
77 kwargs.setdefault('script', mdesc.script())
78 return template % kwargs
79
80def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
81
82 class BaseTsunami(Tsunami):
83 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
84 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
85 pci_func=0, pci_dev=0, pci_bus=0)
86
87 self = LinuxAlphaSystem()
88 if not mdesc:
89 # generic system
90 mdesc = SysConfig()
91 self.readfile = mdesc.script()
92
93 self.tsunami = BaseTsunami()
94
95 # Create the io bus to connect all device ports
96 self.iobus = IOXBar()
97 self.tsunami.attachIO(self.iobus)
98
99 self.tsunami.ide.pio = self.iobus.master
100
101 self.tsunami.ethernet.pio = self.iobus.master
102
103 if ruby:
104 # Store the dma devices for later connection to dma ruby ports.
105 # Append an underscore to dma_ports to avoid the SimObjectVector check.
106 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
107 else:
108 self.membus = MemBus()
109
110 # By default the bridge responds to all addresses above the I/O
111 # base address (including the PCI config space)
112 IO_address_space_base = 0x80000000000
113 self.bridge = Bridge(delay='50ns',
114 ranges = [AddrRange(IO_address_space_base, Addr.max)])
115 self.bridge.master = self.iobus.slave
116 self.bridge.slave = self.membus.master
117
118 self.tsunami.ide.dma = self.iobus.slave
119 self.tsunami.ethernet.dma = self.iobus.slave
120
121 self.system_port = self.membus.slave
122
123 self.mem_ranges = [AddrRange(mdesc.mem())]
124 self.disk0 = CowIdeDisk(driveID='master')
125 self.disk2 = CowIdeDisk(driveID='master')
126 self.disk0.childImage(mdesc.disk())
127 self.disk2.childImage(disk('linux-bigswap2.img'))
128 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
129 read_only = True))
130 self.intrctrl = IntrControl()
131 self.mem_mode = mem_mode
132 self.terminal = Terminal()
133 self.kernel = binary('vmlinux')
134 self.pal = binary('ts_osfpal')
135 self.console = binary('console')
136 if not cmdline:
137 cmdline = 'root=/dev/hda1 console=ttyS0'
138 self.boot_osflags = fillInCmdline(mdesc, cmdline)
139
140 return self
141
142def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
143 # Constants from iob.cc and uart8250.cc
144 iob_man_addr = 0x9800000000
145 uart_pio_size = 8
146
147 class CowMmDisk(MmDisk):
148 image = CowDiskImage(child=RawDiskImage(read_only=True),
149 read_only=False)
150
151 def childImage(self, ci):
152 self.image.child.image_file = ci
153
154 self = SparcSystem()
155 if not mdesc:
156 # generic system
157 mdesc = SysConfig()
158 self.readfile = mdesc.script()
159 self.iobus = IOXBar()
160 self.membus = MemBus()
161 self.bridge = Bridge(delay='50ns')
162 self.t1000 = T1000()
163 self.t1000.attachOnChipIO(self.membus)
164 self.t1000.attachIO(self.iobus)
165 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
166 AddrRange(Addr('2GB'), size ='256MB')]
167 self.bridge.master = self.iobus.slave
168 self.bridge.slave = self.membus.master
169 self.rom.port = self.membus.master
170 self.nvram.port = self.membus.master
171 self.hypervisor_desc.port = self.membus.master
172 self.partition_desc.port = self.membus.master
173 self.intrctrl = IntrControl()
174 self.disk0 = CowMmDisk()
175 self.disk0.childImage(mdesc.disk())
176 self.disk0.pio = self.iobus.master
177
178 # The puart0 and hvuart are placed on the IO bus, so create ranges
179 # for them. The remaining IO range is rather fragmented, so poke
180 # holes for the iob and partition descriptors etc.
181 self.bridge.ranges = \
182 [
183 AddrRange(self.t1000.puart0.pio_addr,
184 self.t1000.puart0.pio_addr + uart_pio_size - 1),
185 AddrRange(self.disk0.pio_addr,
186 self.t1000.fake_jbi.pio_addr +
187 self.t1000.fake_jbi.pio_size - 1),
188 AddrRange(self.t1000.fake_clk.pio_addr,
189 iob_man_addr - 1),
190 AddrRange(self.t1000.fake_l2_1.pio_addr,
191 self.t1000.fake_ssi.pio_addr +
192 self.t1000.fake_ssi.pio_size - 1),
193 AddrRange(self.t1000.hvuart.pio_addr,
194 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
195 ]
196 self.reset_bin = binary('reset_new.bin')
197 self.hypervisor_bin = binary('q_new.bin')
198 self.openboot_bin = binary('openboot_new.bin')
199 self.nvram_bin = binary('nvram1')
200 self.hypervisor_desc_bin = binary('1up-hv.bin')
201 self.partition_desc_bin = binary('1up-md.bin')
202
203 self.system_port = self.membus.slave
204
205 return self
206
207def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
208 dtb_filename=None, bare_metal=False, cmdline=None,
209 external_memory="", ruby=False, security=False):
210 assert machine_type
211
212 pci_devices = []
213
214 if bare_metal:
215 self = ArmSystem()
216 else:
217 self = LinuxArmSystem()
218
219 if not mdesc:
220 # generic system
221 mdesc = SysConfig()
222
223 self.readfile = mdesc.script()
224 self.iobus = IOXBar()
225 if not ruby:
226 self.bridge = Bridge(delay='50ns')
227 self.bridge.master = self.iobus.slave
228 self.membus = MemBus()
229 self.membus.badaddr_responder.warn_access = "warn"
230 self.bridge.slave = self.membus.master
231
232 self.mem_mode = mem_mode
233
234 platform_class = PlatformConfig.get(machine_type)
235 # Resolve the real platform name, the original machine_type
236 # variable might have been an alias.
237 machine_type = platform_class.__name__
238 self.realview = platform_class()
239
240 if isinstance(self.realview, VExpress_EMM64):
241 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
242 print("Selected 64-bit ARM architecture, updating default "
243 "disk image...")
244 mdesc.diskname = 'linaro-minimal-aarch64.img'
245
246
247 # Attach any PCI devices this platform supports
248 self.realview.attachPciDevices()
249
250 self.cf0 = CowIdeDisk(driveID='master')
251 self.cf0.childImage(mdesc.disk())
252 # Old platforms have a built-in IDE or CF controller. Default to
253 # the IDE controller if both exist. New platforms expect the
254 # storage controller to be added from the config script.
255 if hasattr(self.realview, "ide"):
256 self.realview.ide.disks = [self.cf0]
257 elif hasattr(self.realview, "cf_ctrl"):
258 self.realview.cf_ctrl.disks = [self.cf0]
259 else:
260 self.pci_ide = IdeController(disks=[self.cf0])
261 pci_devices.append(self.pci_ide)
262
263 self.mem_ranges = []
264 size_remain = long(Addr(mdesc.mem()))
265 for region in self.realview._mem_regions:
266 if size_remain > long(region.size()):
267 self.mem_ranges.append(region)
268 size_remain = size_remain - long(region.size())
269 else:
270 self.mem_ranges.append(AddrRange(region.start, size=size_remain))
271 size_remain = 0
272 break
273 warn("Memory size specified spans more than one region. Creating" \
274 " another memory controller for that range.")
275
276 if size_remain > 0:
277 fatal("The currently selected ARM platforms doesn't support" \
278 " the amount of DRAM you've selected. Please try" \
279 " another platform")
280
281 self.have_security = security
282
283 if bare_metal:
284 # EOT character on UART will end the simulation
285 self.realview.uart[0].end_on_eot = True
286 else:
287 if dtb_filename:
288 self.dtb_filename = binary(dtb_filename)
289
290 self.machine_type = machine_type if machine_type in ArmMachineType.map \
291 else "DTOnly"
292
293 # Ensure that writes to the UART actually go out early in the boot
294 if not cmdline:
295 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
296 'lpj=19988480 norandmaps rw loglevel=8 ' + \
297 'mem=%(mem)s root=%(rootdev)s'
298
299 # When using external memory, gem5 writes the boot loader to nvmem
300 # and then SST will read from it, but SST can only get to nvmem from
301 # iobus, as gem5's membus is only used for initialization and
302 # SST doesn't use it. Attaching nvmem to iobus solves this issue.
303 # During initialization, system_port -> membus -> iobus -> nvmem.
304 if external_memory:
305 self.realview.setupBootLoader(self.iobus, self, binary)
306 elif ruby:
307 self.realview.setupBootLoader(None, self, binary)
308 else:
309 self.realview.setupBootLoader(self.membus, self, binary)
310
311 if hasattr(self.realview.gic, 'cpu_addr'):
312 self.gic_cpu_addr = self.realview.gic.cpu_addr
313
314 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
315
316 # This check is for users who have previously put 'android' in
317 # the disk image filename to tell the config scripts to
318 # prepare the kernel with android-specific boot options. That
319 # behavior has been replaced with a more explicit option per
320 # the error message below. The disk can have any name now and
321 # doesn't need to include 'android' substring.
322 if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
323 if 'android' not in mdesc.os_type():
324 fatal("It looks like you are trying to boot an Android " \
325 "platform. To boot Android, you must specify " \
326 "--os-type with an appropriate Android release on " \
327 "the command line.")
328
329 # android-specific tweaks
330 if 'android' in mdesc.os_type():
331 # generic tweaks
332 cmdline += " init=/init"
333
334 # release-specific tweaks
335 if 'kitkat' in mdesc.os_type():
336 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
337 "android.bootanim=0 "
338 elif 'nougat' in mdesc.os_type():
339 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
340 "android.bootanim=0 " + \
341 "vmalloc=640MB " + \
342 "android.early.fstab=/fstab.gem5 " + \
343 "androidboot.selinux=permissive " + \
344 "video=Virtual-1:1920x1080-16"
345
346 self.boot_osflags = fillInCmdline(mdesc, cmdline)
347
348 if external_memory:
349 # I/O traffic enters iobus
350 self.external_io = ExternalMaster(port_data="external_io",
351 port_type=external_memory)
352 self.external_io.port = self.iobus.slave
353
354 # Ensure iocache only receives traffic destined for (actual) memory.
355 self.iocache = ExternalSlave(port_data="iocache",
356 port_type=external_memory,
357 addr_ranges=self.mem_ranges)
358 self.iocache.port = self.iobus.master
359
360 # Let system_port get to nvmem and nothing else.
361 self.bridge.ranges = [self.realview.nvmem.range]
362
363 self.realview.attachOnChipIO(self.iobus)
364 # Attach off-chip devices
365 self.realview.attachIO(self.iobus)
366 elif ruby:
367 self._dma_ports = [ ]
368 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
369 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
370 else:
371 self.realview.attachOnChipIO(self.membus, self.bridge)
372 # Attach off-chip devices
373 self.realview.attachIO(self.iobus)
374
375 for dev_id, dev in enumerate(pci_devices):
376 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
377 self.realview.attachPciDevice(
378 dev, self.iobus,
379 dma_ports=self._dma_ports if ruby else None)
380
381 self.intrctrl = IntrControl()
382 self.terminal = Terminal()
383 self.vncserver = VncServer()
384
385 if not ruby:
386 self.system_port = self.membus.slave
387
388 if ruby:
389 if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
390 fatal("The MI_example protocol cannot implement Load/Store "
391 "Exclusive operations. Multicore ARM systems configured "
392 "with the MI_example protocol will not work properly.")
393 warn("You are trying to use Ruby on ARM, which is not working "
394 "properly yet.")
395
396 return self
397
398
399def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
400 class BaseMalta(Malta):
401 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
402 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
403 pci_func=0, pci_dev=0, pci_bus=0)
404
405 self = LinuxMipsSystem()
406 if not mdesc:
407 # generic system
408 mdesc = SysConfig()
409 self.readfile = mdesc.script()
410 self.iobus = IOXBar()
411 self.membus = MemBus()
412 self.bridge = Bridge(delay='50ns')
413 self.mem_ranges = [AddrRange('1GB')]
414 self.bridge.master = self.iobus.slave
415 self.bridge.slave = self.membus.master
416 self.disk0 = CowIdeDisk(driveID='master')
417 self.disk2 = CowIdeDisk(driveID='master')
418 self.disk0.childImage(mdesc.disk())
419 self.disk2.childImage(disk('linux-bigswap2.img'))
420 self.malta = BaseMalta()
421 self.malta.attachIO(self.iobus)
422 self.malta.ide.pio = self.iobus.master
423 self.malta.ide.dma = self.iobus.slave
424 self.malta.ethernet.pio = self.iobus.master
425 self.malta.ethernet.dma = self.iobus.slave
426 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
427 read_only = True))
428 self.intrctrl = IntrControl()
429 self.mem_mode = mem_mode
430 self.terminal = Terminal()
431 self.kernel = binary('mips/vmlinux')
432 self.console = binary('mips/console')
433 if not cmdline:
434 cmdline = 'root=/dev/hda1 console=ttyS0'
435 self.boot_osflags = fillInCmdline(mdesc, cmdline)
436
437 self.system_port = self.membus.slave
438
439 return self
440
441def x86IOAddress(port):
442 IO_address_space_base = 0x8000000000000000
443 return IO_address_space_base + port
444
445def connectX86ClassicSystem(x86_sys, numCPUs):
446 # Constants similar to x86_traits.hh
447 IO_address_space_base = 0x8000000000000000
448 pci_config_address_space_base = 0xc000000000000000
449 interrupts_address_space_base = 0xa000000000000000
450 APIC_range_size = 1 << 12;
451
452 x86_sys.membus = MemBus()
453
454 # North Bridge
455 x86_sys.iobus = IOXBar()
456 x86_sys.bridge = Bridge(delay='50ns')
457 x86_sys.bridge.master = x86_sys.iobus.slave
458 x86_sys.bridge.slave = x86_sys.membus.master
459 # Allow the bridge to pass through:
460 # 1) kernel configured PCI device memory map address: address range
461 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
462 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
463 # 3) everything in the IO address range up to the local APIC, and
464 # 4) then the entire PCI address space and beyond.
465 x86_sys.bridge.ranges = \
466 [
467 AddrRange(0xC0000000, 0xFFFF0000),
468 AddrRange(IO_address_space_base,
469 interrupts_address_space_base - 1),
470 AddrRange(pci_config_address_space_base,
471 Addr.max)
472 ]
473
474 # Create a bridge from the IO bus to the memory bus to allow access to
475 # the local APIC (two pages)
476 x86_sys.apicbridge = Bridge(delay='50ns')
477 x86_sys.apicbridge.slave = x86_sys.iobus.master
478 x86_sys.apicbridge.master = x86_sys.membus.slave
479 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
480 interrupts_address_space_base +
481 numCPUs * APIC_range_size
482 - 1)]
483
484 # connect the io bus
485 x86_sys.pc.attachIO(x86_sys.iobus)
486
487 x86_sys.system_port = x86_sys.membus.slave
488
489def connectX86RubySystem(x86_sys):
490 # North Bridge
491 x86_sys.iobus = IOXBar()
492
493 # add the ide to the list of dma devices that later need to attach to
494 # dma controllers
495 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
496 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
497
498
499def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
500 if self == None:
501 self = X86System()
502
503 if not mdesc:
504 # generic system
505 mdesc = SysConfig()
506 self.readfile = mdesc.script()
507
508 self.mem_mode = mem_mode
509
510 # Physical memory
511 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
512 # for various devices. Hence, if the physical memory size is greater than
513 # 3GB, we need to split it into two parts.
514 excess_mem_size = \
515 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
516 if excess_mem_size <= 0:
517 self.mem_ranges = [AddrRange(mdesc.mem())]
518 else:
519 warn("Physical memory size specified is %s which is greater than " \
520 "3GB. Twice the number of memory controllers would be " \
521 "created." % (mdesc.mem()))
522
523 self.mem_ranges = [AddrRange('3GB'),
524 AddrRange(Addr('4GB'), size = excess_mem_size)]
525
526 # Platform
527 self.pc = Pc()
528
529 # Create and connect the busses required by each memory system
530 if Ruby:
531 connectX86RubySystem(self)
532 else:
533 connectX86ClassicSystem(self, numCPUs)
534
535 self.intrctrl = IntrControl()
536
537 # Disks
538 disk0 = CowIdeDisk(driveID='master')
539 disk2 = CowIdeDisk(driveID='master')
540 disk0.childImage(mdesc.disk())
541 disk2.childImage(disk('linux-bigswap2.img'))
542 self.pc.south_bridge.ide.disks = [disk0, disk2]
543
544 # Add in a Bios information structure.
545 structures = [X86SMBiosBiosInformation()]
546 self.smbios_table.structures = structures
547
548 # Set up the Intel MP table
549 base_entries = []
550 ext_entries = []
| 1# Copyright (c) 2010-2012, 2015-2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from __future__ import print_function
43
44from m5.objects import *
45from Benchmarks import *
46from m5.util import *
47from common import PlatformConfig
48
49# Populate to reflect supported os types per target ISA
50os_types = { 'alpha' : [ 'linux' ],
51 'mips' : [ 'linux' ],
52 'sparc' : [ 'linux' ],
53 'x86' : [ 'linux' ],
54 'arm' : [ 'linux',
55 'android-gingerbread',
56 'android-ics',
57 'android-jellybean',
58 'android-kitkat',
59 'android-nougat', ],
60 }
61
62class CowIdeDisk(IdeDisk):
63 image = CowDiskImage(child=RawDiskImage(read_only=True),
64 read_only=False)
65
66 def childImage(self, ci):
67 self.image.child.image_file = ci
68
69class MemBus(SystemXBar):
70 badaddr_responder = BadAddr()
71 default = Self.badaddr_responder.pio
72
73def fillInCmdline(mdesc, template, **kwargs):
74 kwargs.setdefault('disk', mdesc.disk())
75 kwargs.setdefault('rootdev', mdesc.rootdev())
76 kwargs.setdefault('mem', mdesc.mem())
77 kwargs.setdefault('script', mdesc.script())
78 return template % kwargs
79
80def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
81
82 class BaseTsunami(Tsunami):
83 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
84 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
85 pci_func=0, pci_dev=0, pci_bus=0)
86
87 self = LinuxAlphaSystem()
88 if not mdesc:
89 # generic system
90 mdesc = SysConfig()
91 self.readfile = mdesc.script()
92
93 self.tsunami = BaseTsunami()
94
95 # Create the io bus to connect all device ports
96 self.iobus = IOXBar()
97 self.tsunami.attachIO(self.iobus)
98
99 self.tsunami.ide.pio = self.iobus.master
100
101 self.tsunami.ethernet.pio = self.iobus.master
102
103 if ruby:
104 # Store the dma devices for later connection to dma ruby ports.
105 # Append an underscore to dma_ports to avoid the SimObjectVector check.
106 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
107 else:
108 self.membus = MemBus()
109
110 # By default the bridge responds to all addresses above the I/O
111 # base address (including the PCI config space)
112 IO_address_space_base = 0x80000000000
113 self.bridge = Bridge(delay='50ns',
114 ranges = [AddrRange(IO_address_space_base, Addr.max)])
115 self.bridge.master = self.iobus.slave
116 self.bridge.slave = self.membus.master
117
118 self.tsunami.ide.dma = self.iobus.slave
119 self.tsunami.ethernet.dma = self.iobus.slave
120
121 self.system_port = self.membus.slave
122
123 self.mem_ranges = [AddrRange(mdesc.mem())]
124 self.disk0 = CowIdeDisk(driveID='master')
125 self.disk2 = CowIdeDisk(driveID='master')
126 self.disk0.childImage(mdesc.disk())
127 self.disk2.childImage(disk('linux-bigswap2.img'))
128 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
129 read_only = True))
130 self.intrctrl = IntrControl()
131 self.mem_mode = mem_mode
132 self.terminal = Terminal()
133 self.kernel = binary('vmlinux')
134 self.pal = binary('ts_osfpal')
135 self.console = binary('console')
136 if not cmdline:
137 cmdline = 'root=/dev/hda1 console=ttyS0'
138 self.boot_osflags = fillInCmdline(mdesc, cmdline)
139
140 return self
141
142def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
143 # Constants from iob.cc and uart8250.cc
144 iob_man_addr = 0x9800000000
145 uart_pio_size = 8
146
147 class CowMmDisk(MmDisk):
148 image = CowDiskImage(child=RawDiskImage(read_only=True),
149 read_only=False)
150
151 def childImage(self, ci):
152 self.image.child.image_file = ci
153
154 self = SparcSystem()
155 if not mdesc:
156 # generic system
157 mdesc = SysConfig()
158 self.readfile = mdesc.script()
159 self.iobus = IOXBar()
160 self.membus = MemBus()
161 self.bridge = Bridge(delay='50ns')
162 self.t1000 = T1000()
163 self.t1000.attachOnChipIO(self.membus)
164 self.t1000.attachIO(self.iobus)
165 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
166 AddrRange(Addr('2GB'), size ='256MB')]
167 self.bridge.master = self.iobus.slave
168 self.bridge.slave = self.membus.master
169 self.rom.port = self.membus.master
170 self.nvram.port = self.membus.master
171 self.hypervisor_desc.port = self.membus.master
172 self.partition_desc.port = self.membus.master
173 self.intrctrl = IntrControl()
174 self.disk0 = CowMmDisk()
175 self.disk0.childImage(mdesc.disk())
176 self.disk0.pio = self.iobus.master
177
178 # The puart0 and hvuart are placed on the IO bus, so create ranges
179 # for them. The remaining IO range is rather fragmented, so poke
180 # holes for the iob and partition descriptors etc.
181 self.bridge.ranges = \
182 [
183 AddrRange(self.t1000.puart0.pio_addr,
184 self.t1000.puart0.pio_addr + uart_pio_size - 1),
185 AddrRange(self.disk0.pio_addr,
186 self.t1000.fake_jbi.pio_addr +
187 self.t1000.fake_jbi.pio_size - 1),
188 AddrRange(self.t1000.fake_clk.pio_addr,
189 iob_man_addr - 1),
190 AddrRange(self.t1000.fake_l2_1.pio_addr,
191 self.t1000.fake_ssi.pio_addr +
192 self.t1000.fake_ssi.pio_size - 1),
193 AddrRange(self.t1000.hvuart.pio_addr,
194 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
195 ]
196 self.reset_bin = binary('reset_new.bin')
197 self.hypervisor_bin = binary('q_new.bin')
198 self.openboot_bin = binary('openboot_new.bin')
199 self.nvram_bin = binary('nvram1')
200 self.hypervisor_desc_bin = binary('1up-hv.bin')
201 self.partition_desc_bin = binary('1up-md.bin')
202
203 self.system_port = self.membus.slave
204
205 return self
206
207def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
208 dtb_filename=None, bare_metal=False, cmdline=None,
209 external_memory="", ruby=False, security=False):
210 assert machine_type
211
212 pci_devices = []
213
214 if bare_metal:
215 self = ArmSystem()
216 else:
217 self = LinuxArmSystem()
218
219 if not mdesc:
220 # generic system
221 mdesc = SysConfig()
222
223 self.readfile = mdesc.script()
224 self.iobus = IOXBar()
225 if not ruby:
226 self.bridge = Bridge(delay='50ns')
227 self.bridge.master = self.iobus.slave
228 self.membus = MemBus()
229 self.membus.badaddr_responder.warn_access = "warn"
230 self.bridge.slave = self.membus.master
231
232 self.mem_mode = mem_mode
233
234 platform_class = PlatformConfig.get(machine_type)
235 # Resolve the real platform name, the original machine_type
236 # variable might have been an alias.
237 machine_type = platform_class.__name__
238 self.realview = platform_class()
239
240 if isinstance(self.realview, VExpress_EMM64):
241 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
242 print("Selected 64-bit ARM architecture, updating default "
243 "disk image...")
244 mdesc.diskname = 'linaro-minimal-aarch64.img'
245
246
247 # Attach any PCI devices this platform supports
248 self.realview.attachPciDevices()
249
250 self.cf0 = CowIdeDisk(driveID='master')
251 self.cf0.childImage(mdesc.disk())
252 # Old platforms have a built-in IDE or CF controller. Default to
253 # the IDE controller if both exist. New platforms expect the
254 # storage controller to be added from the config script.
255 if hasattr(self.realview, "ide"):
256 self.realview.ide.disks = [self.cf0]
257 elif hasattr(self.realview, "cf_ctrl"):
258 self.realview.cf_ctrl.disks = [self.cf0]
259 else:
260 self.pci_ide = IdeController(disks=[self.cf0])
261 pci_devices.append(self.pci_ide)
262
263 self.mem_ranges = []
264 size_remain = long(Addr(mdesc.mem()))
265 for region in self.realview._mem_regions:
266 if size_remain > long(region.size()):
267 self.mem_ranges.append(region)
268 size_remain = size_remain - long(region.size())
269 else:
270 self.mem_ranges.append(AddrRange(region.start, size=size_remain))
271 size_remain = 0
272 break
273 warn("Memory size specified spans more than one region. Creating" \
274 " another memory controller for that range.")
275
276 if size_remain > 0:
277 fatal("The currently selected ARM platforms doesn't support" \
278 " the amount of DRAM you've selected. Please try" \
279 " another platform")
280
281 self.have_security = security
282
283 if bare_metal:
284 # EOT character on UART will end the simulation
285 self.realview.uart[0].end_on_eot = True
286 else:
287 if dtb_filename:
288 self.dtb_filename = binary(dtb_filename)
289
290 self.machine_type = machine_type if machine_type in ArmMachineType.map \
291 else "DTOnly"
292
293 # Ensure that writes to the UART actually go out early in the boot
294 if not cmdline:
295 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
296 'lpj=19988480 norandmaps rw loglevel=8 ' + \
297 'mem=%(mem)s root=%(rootdev)s'
298
299 # When using external memory, gem5 writes the boot loader to nvmem
300 # and then SST will read from it, but SST can only get to nvmem from
301 # iobus, as gem5's membus is only used for initialization and
302 # SST doesn't use it. Attaching nvmem to iobus solves this issue.
303 # During initialization, system_port -> membus -> iobus -> nvmem.
304 if external_memory:
305 self.realview.setupBootLoader(self.iobus, self, binary)
306 elif ruby:
307 self.realview.setupBootLoader(None, self, binary)
308 else:
309 self.realview.setupBootLoader(self.membus, self, binary)
310
311 if hasattr(self.realview.gic, 'cpu_addr'):
312 self.gic_cpu_addr = self.realview.gic.cpu_addr
313
314 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
315
316 # This check is for users who have previously put 'android' in
317 # the disk image filename to tell the config scripts to
318 # prepare the kernel with android-specific boot options. That
319 # behavior has been replaced with a more explicit option per
320 # the error message below. The disk can have any name now and
321 # doesn't need to include 'android' substring.
322 if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
323 if 'android' not in mdesc.os_type():
324 fatal("It looks like you are trying to boot an Android " \
325 "platform. To boot Android, you must specify " \
326 "--os-type with an appropriate Android release on " \
327 "the command line.")
328
329 # android-specific tweaks
330 if 'android' in mdesc.os_type():
331 # generic tweaks
332 cmdline += " init=/init"
333
334 # release-specific tweaks
335 if 'kitkat' in mdesc.os_type():
336 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
337 "android.bootanim=0 "
338 elif 'nougat' in mdesc.os_type():
339 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
340 "android.bootanim=0 " + \
341 "vmalloc=640MB " + \
342 "android.early.fstab=/fstab.gem5 " + \
343 "androidboot.selinux=permissive " + \
344 "video=Virtual-1:1920x1080-16"
345
346 self.boot_osflags = fillInCmdline(mdesc, cmdline)
347
348 if external_memory:
349 # I/O traffic enters iobus
350 self.external_io = ExternalMaster(port_data="external_io",
351 port_type=external_memory)
352 self.external_io.port = self.iobus.slave
353
354 # Ensure iocache only receives traffic destined for (actual) memory.
355 self.iocache = ExternalSlave(port_data="iocache",
356 port_type=external_memory,
357 addr_ranges=self.mem_ranges)
358 self.iocache.port = self.iobus.master
359
360 # Let system_port get to nvmem and nothing else.
361 self.bridge.ranges = [self.realview.nvmem.range]
362
363 self.realview.attachOnChipIO(self.iobus)
364 # Attach off-chip devices
365 self.realview.attachIO(self.iobus)
366 elif ruby:
367 self._dma_ports = [ ]
368 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
369 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
370 else:
371 self.realview.attachOnChipIO(self.membus, self.bridge)
372 # Attach off-chip devices
373 self.realview.attachIO(self.iobus)
374
375 for dev_id, dev in enumerate(pci_devices):
376 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
377 self.realview.attachPciDevice(
378 dev, self.iobus,
379 dma_ports=self._dma_ports if ruby else None)
380
381 self.intrctrl = IntrControl()
382 self.terminal = Terminal()
383 self.vncserver = VncServer()
384
385 if not ruby:
386 self.system_port = self.membus.slave
387
388 if ruby:
389 if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
390 fatal("The MI_example protocol cannot implement Load/Store "
391 "Exclusive operations. Multicore ARM systems configured "
392 "with the MI_example protocol will not work properly.")
393 warn("You are trying to use Ruby on ARM, which is not working "
394 "properly yet.")
395
396 return self
397
398
399def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
400 class BaseMalta(Malta):
401 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
402 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
403 pci_func=0, pci_dev=0, pci_bus=0)
404
405 self = LinuxMipsSystem()
406 if not mdesc:
407 # generic system
408 mdesc = SysConfig()
409 self.readfile = mdesc.script()
410 self.iobus = IOXBar()
411 self.membus = MemBus()
412 self.bridge = Bridge(delay='50ns')
413 self.mem_ranges = [AddrRange('1GB')]
414 self.bridge.master = self.iobus.slave
415 self.bridge.slave = self.membus.master
416 self.disk0 = CowIdeDisk(driveID='master')
417 self.disk2 = CowIdeDisk(driveID='master')
418 self.disk0.childImage(mdesc.disk())
419 self.disk2.childImage(disk('linux-bigswap2.img'))
420 self.malta = BaseMalta()
421 self.malta.attachIO(self.iobus)
422 self.malta.ide.pio = self.iobus.master
423 self.malta.ide.dma = self.iobus.slave
424 self.malta.ethernet.pio = self.iobus.master
425 self.malta.ethernet.dma = self.iobus.slave
426 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
427 read_only = True))
428 self.intrctrl = IntrControl()
429 self.mem_mode = mem_mode
430 self.terminal = Terminal()
431 self.kernel = binary('mips/vmlinux')
432 self.console = binary('mips/console')
433 if not cmdline:
434 cmdline = 'root=/dev/hda1 console=ttyS0'
435 self.boot_osflags = fillInCmdline(mdesc, cmdline)
436
437 self.system_port = self.membus.slave
438
439 return self
440
441def x86IOAddress(port):
442 IO_address_space_base = 0x8000000000000000
443 return IO_address_space_base + port
444
445def connectX86ClassicSystem(x86_sys, numCPUs):
446 # Constants similar to x86_traits.hh
447 IO_address_space_base = 0x8000000000000000
448 pci_config_address_space_base = 0xc000000000000000
449 interrupts_address_space_base = 0xa000000000000000
450 APIC_range_size = 1 << 12;
451
452 x86_sys.membus = MemBus()
453
454 # North Bridge
455 x86_sys.iobus = IOXBar()
456 x86_sys.bridge = Bridge(delay='50ns')
457 x86_sys.bridge.master = x86_sys.iobus.slave
458 x86_sys.bridge.slave = x86_sys.membus.master
459 # Allow the bridge to pass through:
460 # 1) kernel configured PCI device memory map address: address range
461 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
462 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
463 # 3) everything in the IO address range up to the local APIC, and
464 # 4) then the entire PCI address space and beyond.
465 x86_sys.bridge.ranges = \
466 [
467 AddrRange(0xC0000000, 0xFFFF0000),
468 AddrRange(IO_address_space_base,
469 interrupts_address_space_base - 1),
470 AddrRange(pci_config_address_space_base,
471 Addr.max)
472 ]
473
474 # Create a bridge from the IO bus to the memory bus to allow access to
475 # the local APIC (two pages)
476 x86_sys.apicbridge = Bridge(delay='50ns')
477 x86_sys.apicbridge.slave = x86_sys.iobus.master
478 x86_sys.apicbridge.master = x86_sys.membus.slave
479 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
480 interrupts_address_space_base +
481 numCPUs * APIC_range_size
482 - 1)]
483
484 # connect the io bus
485 x86_sys.pc.attachIO(x86_sys.iobus)
486
487 x86_sys.system_port = x86_sys.membus.slave
488
489def connectX86RubySystem(x86_sys):
490 # North Bridge
491 x86_sys.iobus = IOXBar()
492
493 # add the ide to the list of dma devices that later need to attach to
494 # dma controllers
495 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
496 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
497
498
499def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
500 if self == None:
501 self = X86System()
502
503 if not mdesc:
504 # generic system
505 mdesc = SysConfig()
506 self.readfile = mdesc.script()
507
508 self.mem_mode = mem_mode
509
510 # Physical memory
511 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
512 # for various devices. Hence, if the physical memory size is greater than
513 # 3GB, we need to split it into two parts.
514 excess_mem_size = \
515 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
516 if excess_mem_size <= 0:
517 self.mem_ranges = [AddrRange(mdesc.mem())]
518 else:
519 warn("Physical memory size specified is %s which is greater than " \
520 "3GB. Twice the number of memory controllers would be " \
521 "created." % (mdesc.mem()))
522
523 self.mem_ranges = [AddrRange('3GB'),
524 AddrRange(Addr('4GB'), size = excess_mem_size)]
525
526 # Platform
527 self.pc = Pc()
528
529 # Create and connect the busses required by each memory system
530 if Ruby:
531 connectX86RubySystem(self)
532 else:
533 connectX86ClassicSystem(self, numCPUs)
534
535 self.intrctrl = IntrControl()
536
537 # Disks
538 disk0 = CowIdeDisk(driveID='master')
539 disk2 = CowIdeDisk(driveID='master')
540 disk0.childImage(mdesc.disk())
541 disk2.childImage(disk('linux-bigswap2.img'))
542 self.pc.south_bridge.ide.disks = [disk0, disk2]
543
544 # Add in a Bios information structure.
545 structures = [X86SMBiosBiosInformation()]
546 self.smbios_table.structures = structures
547
548 # Set up the Intel MP table
549 base_entries = []
550 ext_entries = []
|
552 bp = X86IntelMPProcessor(
553 local_apic_id = i,
554 local_apic_version = 0x14,
555 enable = True,
556 bootstrap = (i == 0))
557 base_entries.append(bp)
558 io_apic = X86IntelMPIOAPIC(
559 id = numCPUs,
560 version = 0x11,
561 enable = True,
562 address = 0xfec00000)
563 self.pc.south_bridge.io_apic.apic_id = io_apic.id
564 base_entries.append(io_apic)
565 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
566 # but linux kernel cannot config PCI device if it was not connected to PCI bus,
567 # so we fix PCI bus id to 0, and ISA bus id to 1.
568 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
569 base_entries.append(pci_bus)
570 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
571 base_entries.append(isa_bus)
572 connect_busses = X86IntelMPBusHierarchy(bus_id=1,
573 subtractive_decode=True, parent_bus=0)
574 ext_entries.append(connect_busses)
575 pci_dev4_inta = X86IntelMPIOIntAssignment(
576 interrupt_type = 'INT',
577 polarity = 'ConformPolarity',
578 trigger = 'ConformTrigger',
579 source_bus_id = 0,
580 source_bus_irq = 0 + (4 << 2),
581 dest_io_apic_id = io_apic.id,
582 dest_io_apic_intin = 16)
583 base_entries.append(pci_dev4_inta)
584 def assignISAInt(irq, apicPin):
585 assign_8259_to_apic = X86IntelMPIOIntAssignment(
586 interrupt_type = 'ExtInt',
587 polarity = 'ConformPolarity',
588 trigger = 'ConformTrigger',
589 source_bus_id = 1,
590 source_bus_irq = irq,
591 dest_io_apic_id = io_apic.id,
592 dest_io_apic_intin = 0)
593 base_entries.append(assign_8259_to_apic)
594 assign_to_apic = X86IntelMPIOIntAssignment(
595 interrupt_type = 'INT',
596 polarity = 'ConformPolarity',
597 trigger = 'ConformTrigger',
598 source_bus_id = 1,
599 source_bus_irq = irq,
600 dest_io_apic_id = io_apic.id,
601 dest_io_apic_intin = apicPin)
602 base_entries.append(assign_to_apic)
603 assignISAInt(0, 2)
604 assignISAInt(1, 1)
605 for i in range(3, 15):
606 assignISAInt(i, i)
607 self.intel_mp_table.base_entries = base_entries
608 self.intel_mp_table.ext_entries = ext_entries
609
610def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
611 cmdline=None):
612 self = LinuxX86System()
613
614 # Build up the x86 system and then specialize it for Linux
615 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
616
617 # We assume below that there's at least 1MB of memory. We'll require 2
618 # just to avoid corner cases.
619 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
620 assert(phys_mem_size >= 0x200000)
621 assert(len(self.mem_ranges) <= 2)
622
623 entries = \
624 [
625 # Mark the first megabyte of memory as reserved
626 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
627 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
628 # Mark the rest of physical memory as available
629 X86E820Entry(addr = 0x100000,
630 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
631 range_type = 1),
632 ]
633
634 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
635 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
636 # specific range can pass though bridge to iobus.
637 if len(self.mem_ranges) == 1:
638 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
639 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
640 range_type=2))
641
642 # Reserve the last 16kB of the 32-bit address space for the m5op interface
643 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
644
645 # In case the physical memory is greater than 3GB, we split it into two
646 # parts and add a separate e820 entry for the second part. This entry
647 # starts at 0x100000000, which is the first address after the space
648 # reserved for devices.
649 if len(self.mem_ranges) == 2:
650 entries.append(X86E820Entry(addr = 0x100000000,
651 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
652
653 self.e820_table.entries = entries
654
655 # Command line
656 if not cmdline:
657 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
658 self.boot_osflags = fillInCmdline(mdesc, cmdline)
659 self.kernel = binary('x86_64-vmlinux-2.6.22.9')
660 return self
661
662
663def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
664 self = Root(full_system = full_system)
665 self.testsys = testSystem
666 self.drivesys = driveSystem
667 self.etherlink = EtherLink()
668
669 if hasattr(testSystem, 'realview'):
670 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
671 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
672 elif hasattr(testSystem, 'tsunami'):
673 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
674 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
675 else:
676 fatal("Don't know how to connect these system together")
677
678 if dumpfile:
679 self.etherdump = EtherDump(file=dumpfile)
680 self.etherlink.dump = Parent.etherdump
681
682 return self
683
684
685def makeDistRoot(testSystem,
686 rank,
687 size,
688 server_name,
689 server_port,
690 sync_repeat,
691 sync_start,
692 linkspeed,
693 linkdelay,
694 dumpfile):
695 self = Root(full_system = True)
696 self.testsys = testSystem
697
698 self.etherlink = DistEtherLink(speed = linkspeed,
699 delay = linkdelay,
700 dist_rank = rank,
701 dist_size = size,
702 server_name = server_name,
703 server_port = server_port,
704 sync_start = sync_start,
705 sync_repeat = sync_repeat)
706
707 if hasattr(testSystem, 'realview'):
708 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
709 elif hasattr(testSystem, 'tsunami'):
710 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
711 else:
712 fatal("Don't know how to connect DistEtherLink to this system")
713
714 if dumpfile:
715 self.etherdump = EtherDump(file=dumpfile)
716 self.etherlink.dump = Parent.etherdump
717
718 return self
| 552 bp = X86IntelMPProcessor(
553 local_apic_id = i,
554 local_apic_version = 0x14,
555 enable = True,
556 bootstrap = (i == 0))
557 base_entries.append(bp)
558 io_apic = X86IntelMPIOAPIC(
559 id = numCPUs,
560 version = 0x11,
561 enable = True,
562 address = 0xfec00000)
563 self.pc.south_bridge.io_apic.apic_id = io_apic.id
564 base_entries.append(io_apic)
565 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
566 # but linux kernel cannot config PCI device if it was not connected to PCI bus,
567 # so we fix PCI bus id to 0, and ISA bus id to 1.
568 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
569 base_entries.append(pci_bus)
570 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
571 base_entries.append(isa_bus)
572 connect_busses = X86IntelMPBusHierarchy(bus_id=1,
573 subtractive_decode=True, parent_bus=0)
574 ext_entries.append(connect_busses)
575 pci_dev4_inta = X86IntelMPIOIntAssignment(
576 interrupt_type = 'INT',
577 polarity = 'ConformPolarity',
578 trigger = 'ConformTrigger',
579 source_bus_id = 0,
580 source_bus_irq = 0 + (4 << 2),
581 dest_io_apic_id = io_apic.id,
582 dest_io_apic_intin = 16)
583 base_entries.append(pci_dev4_inta)
584 def assignISAInt(irq, apicPin):
585 assign_8259_to_apic = X86IntelMPIOIntAssignment(
586 interrupt_type = 'ExtInt',
587 polarity = 'ConformPolarity',
588 trigger = 'ConformTrigger',
589 source_bus_id = 1,
590 source_bus_irq = irq,
591 dest_io_apic_id = io_apic.id,
592 dest_io_apic_intin = 0)
593 base_entries.append(assign_8259_to_apic)
594 assign_to_apic = X86IntelMPIOIntAssignment(
595 interrupt_type = 'INT',
596 polarity = 'ConformPolarity',
597 trigger = 'ConformTrigger',
598 source_bus_id = 1,
599 source_bus_irq = irq,
600 dest_io_apic_id = io_apic.id,
601 dest_io_apic_intin = apicPin)
602 base_entries.append(assign_to_apic)
603 assignISAInt(0, 2)
604 assignISAInt(1, 1)
605 for i in range(3, 15):
606 assignISAInt(i, i)
607 self.intel_mp_table.base_entries = base_entries
608 self.intel_mp_table.ext_entries = ext_entries
609
610def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
611 cmdline=None):
612 self = LinuxX86System()
613
614 # Build up the x86 system and then specialize it for Linux
615 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
616
617 # We assume below that there's at least 1MB of memory. We'll require 2
618 # just to avoid corner cases.
619 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
620 assert(phys_mem_size >= 0x200000)
621 assert(len(self.mem_ranges) <= 2)
622
623 entries = \
624 [
625 # Mark the first megabyte of memory as reserved
626 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
627 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
628 # Mark the rest of physical memory as available
629 X86E820Entry(addr = 0x100000,
630 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
631 range_type = 1),
632 ]
633
634 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
635 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
636 # specific range can pass though bridge to iobus.
637 if len(self.mem_ranges) == 1:
638 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
639 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
640 range_type=2))
641
642 # Reserve the last 16kB of the 32-bit address space for the m5op interface
643 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
644
645 # In case the physical memory is greater than 3GB, we split it into two
646 # parts and add a separate e820 entry for the second part. This entry
647 # starts at 0x100000000, which is the first address after the space
648 # reserved for devices.
649 if len(self.mem_ranges) == 2:
650 entries.append(X86E820Entry(addr = 0x100000000,
651 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
652
653 self.e820_table.entries = entries
654
655 # Command line
656 if not cmdline:
657 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
658 self.boot_osflags = fillInCmdline(mdesc, cmdline)
659 self.kernel = binary('x86_64-vmlinux-2.6.22.9')
660 return self
661
662
663def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
664 self = Root(full_system = full_system)
665 self.testsys = testSystem
666 self.drivesys = driveSystem
667 self.etherlink = EtherLink()
668
669 if hasattr(testSystem, 'realview'):
670 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
671 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
672 elif hasattr(testSystem, 'tsunami'):
673 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
674 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
675 else:
676 fatal("Don't know how to connect these system together")
677
678 if dumpfile:
679 self.etherdump = EtherDump(file=dumpfile)
680 self.etherlink.dump = Parent.etherdump
681
682 return self
683
684
685def makeDistRoot(testSystem,
686 rank,
687 size,
688 server_name,
689 server_port,
690 sync_repeat,
691 sync_start,
692 linkspeed,
693 linkdelay,
694 dumpfile):
695 self = Root(full_system = True)
696 self.testsys = testSystem
697
698 self.etherlink = DistEtherLink(speed = linkspeed,
699 delay = linkdelay,
700 dist_rank = rank,
701 dist_size = size,
702 server_name = server_name,
703 server_port = server_port,
704 sync_start = sync_start,
705 sync_repeat = sync_repeat)
706
707 if hasattr(testSystem, 'realview'):
708 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
709 elif hasattr(testSystem, 'tsunami'):
710 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
711 else:
712 fatal("Don't know how to connect DistEtherLink to this system")
713
714 if dumpfile:
715 self.etherdump = EtherDump(file=dumpfile)
716 self.etherlink.dump = Parent.etherdump
717
718 return self
|