46
47# Populate to reflect supported os types per target ISA
48os_types = { 'alpha' : [ 'linux' ],
49 'mips' : [ 'linux' ],
50 'sparc' : [ 'linux' ],
51 'x86' : [ 'linux' ],
52 'arm' : [ 'linux',
53 'android-gingerbread',
54 'android-ics',
55 'android-jellybean',
56 'android-kitkat' ],
57 }
58
59class CowIdeDisk(IdeDisk):
60 image = CowDiskImage(child=RawDiskImage(read_only=True),
61 read_only=False)
62
63 def childImage(self, ci):
64 self.image.child.image_file = ci
65
66class MemBus(SystemXBar):
67 badaddr_responder = BadAddr()
68 default = Self.badaddr_responder.pio
69
70def fillInCmdline(mdesc, template, **kwargs):
71 kwargs.setdefault('disk', mdesc.disk())
72 kwargs.setdefault('rootdev', mdesc.rootdev())
73 kwargs.setdefault('mem', mdesc.mem())
74 kwargs.setdefault('script', mdesc.script())
75 return template % kwargs
76
77def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
78
79 class BaseTsunami(Tsunami):
80 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
81 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
82 pci_func=0, pci_dev=0, pci_bus=0)
83
84 self = LinuxAlphaSystem()
85 if not mdesc:
86 # generic system
87 mdesc = SysConfig()
88 self.readfile = mdesc.script()
89
90 self.tsunami = BaseTsunami()
91
92 # Create the io bus to connect all device ports
93 self.iobus = IOXBar()
94 self.tsunami.attachIO(self.iobus)
95
96 self.tsunami.ide.pio = self.iobus.master
97
98 self.tsunami.ethernet.pio = self.iobus.master
99
100 if ruby:
101 # Store the dma devices for later connection to dma ruby ports.
102 # Append an underscore to dma_ports to avoid the SimObjectVector check.
103 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
104 else:
105 self.membus = MemBus()
106
107 # By default the bridge responds to all addresses above the I/O
108 # base address (including the PCI config space)
109 IO_address_space_base = 0x80000000000
110 self.bridge = Bridge(delay='50ns',
111 ranges = [AddrRange(IO_address_space_base, Addr.max)])
112 self.bridge.master = self.iobus.slave
113 self.bridge.slave = self.membus.master
114
115 self.tsunami.ide.dma = self.iobus.slave
116 self.tsunami.ethernet.dma = self.iobus.slave
117
118 self.system_port = self.membus.slave
119
120 self.mem_ranges = [AddrRange(mdesc.mem())]
121 self.disk0 = CowIdeDisk(driveID='master')
122 self.disk2 = CowIdeDisk(driveID='master')
123 self.disk0.childImage(mdesc.disk())
124 self.disk2.childImage(disk('linux-bigswap2.img'))
125 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
126 read_only = True))
127 self.intrctrl = IntrControl()
128 self.mem_mode = mem_mode
129 self.terminal = Terminal()
130 self.kernel = binary('vmlinux')
131 self.pal = binary('ts_osfpal')
132 self.console = binary('console')
133 if not cmdline:
134 cmdline = 'root=/dev/hda1 console=ttyS0'
135 self.boot_osflags = fillInCmdline(mdesc, cmdline)
136
137 return self
138
139def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
140 # Constants from iob.cc and uart8250.cc
141 iob_man_addr = 0x9800000000
142 uart_pio_size = 8
143
144 class CowMmDisk(MmDisk):
145 image = CowDiskImage(child=RawDiskImage(read_only=True),
146 read_only=False)
147
148 def childImage(self, ci):
149 self.image.child.image_file = ci
150
151 self = SparcSystem()
152 if not mdesc:
153 # generic system
154 mdesc = SysConfig()
155 self.readfile = mdesc.script()
156 self.iobus = IOXBar()
157 self.membus = MemBus()
158 self.bridge = Bridge(delay='50ns')
159 self.t1000 = T1000()
160 self.t1000.attachOnChipIO(self.membus)
161 self.t1000.attachIO(self.iobus)
162 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
163 AddrRange(Addr('2GB'), size ='256MB')]
164 self.bridge.master = self.iobus.slave
165 self.bridge.slave = self.membus.master
166 self.rom.port = self.membus.master
167 self.nvram.port = self.membus.master
168 self.hypervisor_desc.port = self.membus.master
169 self.partition_desc.port = self.membus.master
170 self.intrctrl = IntrControl()
171 self.disk0 = CowMmDisk()
172 self.disk0.childImage(mdesc.disk())
173 self.disk0.pio = self.iobus.master
174
175 # The puart0 and hvuart are placed on the IO bus, so create ranges
176 # for them. The remaining IO range is rather fragmented, so poke
177 # holes for the iob and partition descriptors etc.
178 self.bridge.ranges = \
179 [
180 AddrRange(self.t1000.puart0.pio_addr,
181 self.t1000.puart0.pio_addr + uart_pio_size - 1),
182 AddrRange(self.disk0.pio_addr,
183 self.t1000.fake_jbi.pio_addr +
184 self.t1000.fake_jbi.pio_size - 1),
185 AddrRange(self.t1000.fake_clk.pio_addr,
186 iob_man_addr - 1),
187 AddrRange(self.t1000.fake_l2_1.pio_addr,
188 self.t1000.fake_ssi.pio_addr +
189 self.t1000.fake_ssi.pio_size - 1),
190 AddrRange(self.t1000.hvuart.pio_addr,
191 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
192 ]
193 self.reset_bin = binary('reset_new.bin')
194 self.hypervisor_bin = binary('q_new.bin')
195 self.openboot_bin = binary('openboot_new.bin')
196 self.nvram_bin = binary('nvram1')
197 self.hypervisor_desc_bin = binary('1up-hv.bin')
198 self.partition_desc_bin = binary('1up-md.bin')
199
200 self.system_port = self.membus.slave
201
202 return self
203
204def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
205 dtb_filename=None, bare_metal=False, cmdline=None,
206 external_memory="", ruby=False):
207 assert machine_type
208
209 default_dtbs = {
210 "RealViewEB": None,
211 "RealViewPBX": None,
212 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus,
213 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
214 }
215
216 default_kernels = {
217 "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8",
218 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8",
219 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5",
220 "VExpress_EMM64": "vmlinux.aarch64.20140821",
221 }
222
223 pci_devices = []
224
225 if bare_metal:
226 self = ArmSystem()
227 else:
228 self = LinuxArmSystem()
229
230 if not mdesc:
231 # generic system
232 mdesc = SysConfig()
233
234 self.readfile = mdesc.script()
235 self.iobus = IOXBar()
236 if not ruby:
237 self.bridge = Bridge(delay='50ns')
238 self.bridge.master = self.iobus.slave
239 self.membus = MemBus()
240 self.membus.badaddr_responder.warn_access = "warn"
241 self.bridge.slave = self.membus.master
242
243 self.mem_mode = mem_mode
244
245 platform_class = PlatformConfig.get(machine_type)
246 # Resolve the real platform name, the original machine_type
247 # variable might have been an alias.
248 machine_type = platform_class.__name__
249 self.realview = platform_class()
250
251 if not dtb_filename and not bare_metal:
252 try:
253 dtb_filename = default_dtbs[machine_type]
254 except KeyError:
255 fatal("No DTB specified and no default DTB known for '%s'" % \
256 machine_type)
257
258 if isinstance(self.realview, VExpress_EMM64):
259 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
260 print "Selected 64-bit ARM architecture, updating default disk image..."
261 mdesc.diskname = 'linaro-minimal-aarch64.img'
262
263
264 # Attach any PCI devices this platform supports
265 self.realview.attachPciDevices()
266
267 self.cf0 = CowIdeDisk(driveID='master')
268 self.cf0.childImage(mdesc.disk())
269 # Old platforms have a built-in IDE or CF controller. Default to
270 # the IDE controller if both exist. New platforms expect the
271 # storage controller to be added from the config script.
272 if hasattr(self.realview, "ide"):
273 self.realview.ide.disks = [self.cf0]
274 elif hasattr(self.realview, "cf_ctrl"):
275 self.realview.cf_ctrl.disks = [self.cf0]
276 else:
277 self.pci_ide = IdeController(disks=[self.cf0])
278 pci_devices.append(self.pci_ide)
279
280 self.mem_ranges = []
281 size_remain = long(Addr(mdesc.mem()))
282 for region in self.realview._mem_regions:
283 if size_remain > long(region[1]):
284 self.mem_ranges.append(AddrRange(region[0], size=region[1]))
285 size_remain = size_remain - long(region[1])
286 else:
287 self.mem_ranges.append(AddrRange(region[0], size=size_remain))
288 size_remain = 0
289 break
290 warn("Memory size specified spans more than one region. Creating" \
291 " another memory controller for that range.")
292
293 if size_remain > 0:
294 fatal("The currently selected ARM platforms doesn't support" \
295 " the amount of DRAM you've selected. Please try" \
296 " another platform")
297
298 if bare_metal:
299 # EOT character on UART will end the simulation
300 self.realview.uart.end_on_eot = True
301 else:
302 if machine_type in default_kernels:
303 self.kernel = binary(default_kernels[machine_type])
304
305 if dtb_filename:
306 self.dtb_filename = binary(dtb_filename)
307
308 self.machine_type = machine_type if machine_type in ArmMachineType.map \
309 else "DTOnly"
310
311 # Ensure that writes to the UART actually go out early in the boot
312 if not cmdline:
313 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
314 'lpj=19988480 norandmaps rw loglevel=8 ' + \
315 'mem=%(mem)s root=%(rootdev)s'
316
317 # When using external memory, gem5 writes the boot loader to nvmem
318 # and then SST will read from it, but SST can only get to nvmem from
319 # iobus, as gem5's membus is only used for initialization and
320 # SST doesn't use it. Attaching nvmem to iobus solves this issue.
321 # During initialization, system_port -> membus -> iobus -> nvmem.
322 if external_memory or ruby:
323 self.realview.setupBootLoader(self.iobus, self, binary)
324 else:
325 self.realview.setupBootLoader(self.membus, self, binary)
326 self.gic_cpu_addr = self.realview.gic.cpu_addr
327 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
328
329 # This check is for users who have previously put 'android' in
330 # the disk image filename to tell the config scripts to
331 # prepare the kernel with android-specific boot options. That
332 # behavior has been replaced with a more explicit option per
333 # the error message below. The disk can have any name now and
334 # doesn't need to include 'android' substring.
335 if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
336 if 'android' not in mdesc.os_type():
337 fatal("It looks like you are trying to boot an Android " \
338 "platform. To boot Android, you must specify " \
339 "--os-type with an appropriate Android release on " \
340 "the command line.")
341
342 # android-specific tweaks
343 if 'android' in mdesc.os_type():
344 # generic tweaks
345 cmdline += " init=/init"
346
347 # release-specific tweaks
348 if 'kitkat' in mdesc.os_type():
349 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
350 "android.bootanim=0"
351
352 self.boot_osflags = fillInCmdline(mdesc, cmdline)
353
354 if external_memory:
355 # I/O traffic enters iobus
356 self.external_io = ExternalMaster(port_data="external_io",
357 port_type=external_memory)
358 self.external_io.port = self.iobus.slave
359
360 # Ensure iocache only receives traffic destined for (actual) memory.
361 self.iocache = ExternalSlave(port_data="iocache",
362 port_type=external_memory,
363 addr_ranges=self.mem_ranges)
364 self.iocache.port = self.iobus.master
365
366 # Let system_port get to nvmem and nothing else.
367 self.bridge.ranges = [self.realview.nvmem.range]
368
369 self.realview.attachOnChipIO(self.iobus)
370 # Attach off-chip devices
371 self.realview.attachIO(self.iobus)
372 elif ruby:
373 self._dma_ports = [ ]
374 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
375 # Force Ruby to treat the boot ROM as an IO device.
376 self.realview.nvmem.in_addr_map = False
377 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
378 else:
379 self.realview.attachOnChipIO(self.membus, self.bridge)
380 # Attach off-chip devices
381 self.realview.attachIO(self.iobus)
382
383 for dev_id, dev in enumerate(pci_devices):
384 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
385 self.realview.attachPciDevice(
386 dev, self.iobus,
387 dma_ports=self._dma_ports if ruby else None)
388
389 self.intrctrl = IntrControl()
390 self.terminal = Terminal()
391 self.vncserver = VncServer()
392
393 if not ruby:
394 self.system_port = self.membus.slave
395
396 if ruby:
397 fatal("You're trying to use Ruby on ARM, which is not working " \
398 "properly yet. If you want to test it anyway, you " \
399 "need to remove this fatal error from FSConfig.py.")
400
401 return self
402
403
404def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
405 class BaseMalta(Malta):
406 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
407 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
408 pci_func=0, pci_dev=0, pci_bus=0)
409
410 self = LinuxMipsSystem()
411 if not mdesc:
412 # generic system
413 mdesc = SysConfig()
414 self.readfile = mdesc.script()
415 self.iobus = IOXBar()
416 self.membus = MemBus()
417 self.bridge = Bridge(delay='50ns')
418 self.mem_ranges = [AddrRange('1GB')]
419 self.bridge.master = self.iobus.slave
420 self.bridge.slave = self.membus.master
421 self.disk0 = CowIdeDisk(driveID='master')
422 self.disk2 = CowIdeDisk(driveID='master')
423 self.disk0.childImage(mdesc.disk())
424 self.disk2.childImage(disk('linux-bigswap2.img'))
425 self.malta = BaseMalta()
426 self.malta.attachIO(self.iobus)
427 self.malta.ide.pio = self.iobus.master
428 self.malta.ide.dma = self.iobus.slave
429 self.malta.ethernet.pio = self.iobus.master
430 self.malta.ethernet.dma = self.iobus.slave
431 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
432 read_only = True))
433 self.intrctrl = IntrControl()
434 self.mem_mode = mem_mode
435 self.terminal = Terminal()
436 self.kernel = binary('mips/vmlinux')
437 self.console = binary('mips/console')
438 if not cmdline:
439 cmdline = 'root=/dev/hda1 console=ttyS0'
440 self.boot_osflags = fillInCmdline(mdesc, cmdline)
441
442 self.system_port = self.membus.slave
443
444 return self
445
446def x86IOAddress(port):
447 IO_address_space_base = 0x8000000000000000
448 return IO_address_space_base + port
449
450def connectX86ClassicSystem(x86_sys, numCPUs):
451 # Constants similar to x86_traits.hh
452 IO_address_space_base = 0x8000000000000000
453 pci_config_address_space_base = 0xc000000000000000
454 interrupts_address_space_base = 0xa000000000000000
455 APIC_range_size = 1 << 12;
456
457 x86_sys.membus = MemBus()
458
459 # North Bridge
460 x86_sys.iobus = IOXBar()
461 x86_sys.bridge = Bridge(delay='50ns')
462 x86_sys.bridge.master = x86_sys.iobus.slave
463 x86_sys.bridge.slave = x86_sys.membus.master
464 # Allow the bridge to pass through:
465 # 1) kernel configured PCI device memory map address: address range
466 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
467 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
468 # 3) everything in the IO address range up to the local APIC, and
469 # 4) then the entire PCI address space and beyond.
470 x86_sys.bridge.ranges = \
471 [
472 AddrRange(0xC0000000, 0xFFFF0000),
473 AddrRange(IO_address_space_base,
474 interrupts_address_space_base - 1),
475 AddrRange(pci_config_address_space_base,
476 Addr.max)
477 ]
478
479 # Create a bridge from the IO bus to the memory bus to allow access to
480 # the local APIC (two pages)
481 x86_sys.apicbridge = Bridge(delay='50ns')
482 x86_sys.apicbridge.slave = x86_sys.iobus.master
483 x86_sys.apicbridge.master = x86_sys.membus.slave
484 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
485 interrupts_address_space_base +
486 numCPUs * APIC_range_size
487 - 1)]
488
489 # connect the io bus
490 x86_sys.pc.attachIO(x86_sys.iobus)
491
492 x86_sys.system_port = x86_sys.membus.slave
493
494def connectX86RubySystem(x86_sys):
495 # North Bridge
496 x86_sys.iobus = IOXBar()
497
498 # add the ide to the list of dma devices that later need to attach to
499 # dma controllers
500 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
501 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
502
503
504def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
505 if self == None:
506 self = X86System()
507
508 if not mdesc:
509 # generic system
510 mdesc = SysConfig()
511 self.readfile = mdesc.script()
512
513 self.mem_mode = mem_mode
514
515 # Physical memory
516 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
517 # for various devices. Hence, if the physical memory size is greater than
518 # 3GB, we need to split it into two parts.
519 excess_mem_size = \
520 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
521 if excess_mem_size <= 0:
522 self.mem_ranges = [AddrRange(mdesc.mem())]
523 else:
524 warn("Physical memory size specified is %s which is greater than " \
525 "3GB. Twice the number of memory controllers would be " \
526 "created." % (mdesc.mem()))
527
528 self.mem_ranges = [AddrRange('3GB'),
529 AddrRange(Addr('4GB'), size = excess_mem_size)]
530
531 # Platform
532 self.pc = Pc()
533
534 # Create and connect the busses required by each memory system
535 if Ruby:
536 connectX86RubySystem(self)
537 else:
538 connectX86ClassicSystem(self, numCPUs)
539
540 self.intrctrl = IntrControl()
541
542 # Disks
543 disk0 = CowIdeDisk(driveID='master')
544 disk2 = CowIdeDisk(driveID='master')
545 disk0.childImage(mdesc.disk())
546 disk2.childImage(disk('linux-bigswap2.img'))
547 self.pc.south_bridge.ide.disks = [disk0, disk2]
548
549 # Add in a Bios information structure.
550 structures = [X86SMBiosBiosInformation()]
551 self.smbios_table.structures = structures
552
553 # Set up the Intel MP table
554 base_entries = []
555 ext_entries = []
556 for i in xrange(numCPUs):
557 bp = X86IntelMPProcessor(
558 local_apic_id = i,
559 local_apic_version = 0x14,
560 enable = True,
561 bootstrap = (i == 0))
562 base_entries.append(bp)
563 io_apic = X86IntelMPIOAPIC(
564 id = numCPUs,
565 version = 0x11,
566 enable = True,
567 address = 0xfec00000)
568 self.pc.south_bridge.io_apic.apic_id = io_apic.id
569 base_entries.append(io_apic)
570 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
571 # but linux kernel cannot config PCI device if it was not connected to PCI bus,
572 # so we fix PCI bus id to 0, and ISA bus id to 1.
573 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
574 base_entries.append(pci_bus)
575 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
576 base_entries.append(isa_bus)
577 connect_busses = X86IntelMPBusHierarchy(bus_id=1,
578 subtractive_decode=True, parent_bus=0)
579 ext_entries.append(connect_busses)
580 pci_dev4_inta = X86IntelMPIOIntAssignment(
581 interrupt_type = 'INT',
582 polarity = 'ConformPolarity',
583 trigger = 'ConformTrigger',
584 source_bus_id = 0,
585 source_bus_irq = 0 + (4 << 2),
586 dest_io_apic_id = io_apic.id,
587 dest_io_apic_intin = 16)
588 base_entries.append(pci_dev4_inta)
589 def assignISAInt(irq, apicPin):
590 assign_8259_to_apic = X86IntelMPIOIntAssignment(
591 interrupt_type = 'ExtInt',
592 polarity = 'ConformPolarity',
593 trigger = 'ConformTrigger',
594 source_bus_id = 1,
595 source_bus_irq = irq,
596 dest_io_apic_id = io_apic.id,
597 dest_io_apic_intin = 0)
598 base_entries.append(assign_8259_to_apic)
599 assign_to_apic = X86IntelMPIOIntAssignment(
600 interrupt_type = 'INT',
601 polarity = 'ConformPolarity',
602 trigger = 'ConformTrigger',
603 source_bus_id = 1,
604 source_bus_irq = irq,
605 dest_io_apic_id = io_apic.id,
606 dest_io_apic_intin = apicPin)
607 base_entries.append(assign_to_apic)
608 assignISAInt(0, 2)
609 assignISAInt(1, 1)
610 for i in range(3, 15):
611 assignISAInt(i, i)
612 self.intel_mp_table.base_entries = base_entries
613 self.intel_mp_table.ext_entries = ext_entries
614
615def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
616 cmdline=None):
617 self = LinuxX86System()
618
619 # Build up the x86 system and then specialize it for Linux
620 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
621
622 # We assume below that there's at least 1MB of memory. We'll require 2
623 # just to avoid corner cases.
624 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
625 assert(phys_mem_size >= 0x200000)
626 assert(len(self.mem_ranges) <= 2)
627
628 entries = \
629 [
630 # Mark the first megabyte of memory as reserved
631 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
632 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
633 # Mark the rest of physical memory as available
634 X86E820Entry(addr = 0x100000,
635 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
636 range_type = 1),
637 ]
638
639 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
640 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
641 # specific range can pass though bridge to iobus.
642 if len(self.mem_ranges) == 1:
643 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
644 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
645 range_type=2))
646
647 # Reserve the last 16kB of the 32-bit address space for the m5op interface
648 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
649
650 # In case the physical memory is greater than 3GB, we split it into two
651 # parts and add a separate e820 entry for the second part. This entry
652 # starts at 0x100000000, which is the first address after the space
653 # reserved for devices.
654 if len(self.mem_ranges) == 2:
655 entries.append(X86E820Entry(addr = 0x100000000,
656 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
657
658 self.e820_table.entries = entries
659
660 # Command line
661 if not cmdline:
662 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
663 self.boot_osflags = fillInCmdline(mdesc, cmdline)
664 self.kernel = binary('x86_64-vmlinux-2.6.22.9')
665 return self
666
667
668def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
669 self = Root(full_system = full_system)
670 self.testsys = testSystem
671 self.drivesys = driveSystem
672 self.etherlink = EtherLink()
673
674 if hasattr(testSystem, 'realview'):
675 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
676 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
677 elif hasattr(testSystem, 'tsunami'):
678 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
679 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
680 else:
681 fatal("Don't know how to connect these system together")
682
683 if dumpfile:
684 self.etherdump = EtherDump(file=dumpfile)
685 self.etherlink.dump = Parent.etherdump
686
687 return self
688
689
690def makeDistRoot(testSystem,
691 rank,
692 size,
693 server_name,
694 server_port,
695 sync_repeat,
696 sync_start,
697 linkspeed,
698 linkdelay,
699 dumpfile):
700 self = Root(full_system = True)
701 self.testsys = testSystem
702
703 self.etherlink = DistEtherLink(speed = linkspeed,
704 delay = linkdelay,
705 dist_rank = rank,
706 dist_size = size,
707 server_name = server_name,
708 server_port = server_port,
709 sync_start = sync_start,
710 sync_repeat = sync_repeat)
711
712 if hasattr(testSystem, 'realview'):
713 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
714 elif hasattr(testSystem, 'tsunami'):
715 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
716 else:
717 fatal("Don't know how to connect DistEtherLink to this system")
718
719 if dumpfile:
720 self.etherdump = EtherDump(file=dumpfile)
721 self.etherlink.dump = Parent.etherdump
722
723 return self
| 46
47# Populate to reflect supported os types per target ISA
48os_types = { 'alpha' : [ 'linux' ],
49 'mips' : [ 'linux' ],
50 'sparc' : [ 'linux' ],
51 'x86' : [ 'linux' ],
52 'arm' : [ 'linux',
53 'android-gingerbread',
54 'android-ics',
55 'android-jellybean',
56 'android-kitkat' ],
57 }
58
59class CowIdeDisk(IdeDisk):
60 image = CowDiskImage(child=RawDiskImage(read_only=True),
61 read_only=False)
62
63 def childImage(self, ci):
64 self.image.child.image_file = ci
65
66class MemBus(SystemXBar):
67 badaddr_responder = BadAddr()
68 default = Self.badaddr_responder.pio
69
70def fillInCmdline(mdesc, template, **kwargs):
71 kwargs.setdefault('disk', mdesc.disk())
72 kwargs.setdefault('rootdev', mdesc.rootdev())
73 kwargs.setdefault('mem', mdesc.mem())
74 kwargs.setdefault('script', mdesc.script())
75 return template % kwargs
76
77def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
78
79 class BaseTsunami(Tsunami):
80 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
81 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
82 pci_func=0, pci_dev=0, pci_bus=0)
83
84 self = LinuxAlphaSystem()
85 if not mdesc:
86 # generic system
87 mdesc = SysConfig()
88 self.readfile = mdesc.script()
89
90 self.tsunami = BaseTsunami()
91
92 # Create the io bus to connect all device ports
93 self.iobus = IOXBar()
94 self.tsunami.attachIO(self.iobus)
95
96 self.tsunami.ide.pio = self.iobus.master
97
98 self.tsunami.ethernet.pio = self.iobus.master
99
100 if ruby:
101 # Store the dma devices for later connection to dma ruby ports.
102 # Append an underscore to dma_ports to avoid the SimObjectVector check.
103 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
104 else:
105 self.membus = MemBus()
106
107 # By default the bridge responds to all addresses above the I/O
108 # base address (including the PCI config space)
109 IO_address_space_base = 0x80000000000
110 self.bridge = Bridge(delay='50ns',
111 ranges = [AddrRange(IO_address_space_base, Addr.max)])
112 self.bridge.master = self.iobus.slave
113 self.bridge.slave = self.membus.master
114
115 self.tsunami.ide.dma = self.iobus.slave
116 self.tsunami.ethernet.dma = self.iobus.slave
117
118 self.system_port = self.membus.slave
119
120 self.mem_ranges = [AddrRange(mdesc.mem())]
121 self.disk0 = CowIdeDisk(driveID='master')
122 self.disk2 = CowIdeDisk(driveID='master')
123 self.disk0.childImage(mdesc.disk())
124 self.disk2.childImage(disk('linux-bigswap2.img'))
125 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
126 read_only = True))
127 self.intrctrl = IntrControl()
128 self.mem_mode = mem_mode
129 self.terminal = Terminal()
130 self.kernel = binary('vmlinux')
131 self.pal = binary('ts_osfpal')
132 self.console = binary('console')
133 if not cmdline:
134 cmdline = 'root=/dev/hda1 console=ttyS0'
135 self.boot_osflags = fillInCmdline(mdesc, cmdline)
136
137 return self
138
139def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
140 # Constants from iob.cc and uart8250.cc
141 iob_man_addr = 0x9800000000
142 uart_pio_size = 8
143
144 class CowMmDisk(MmDisk):
145 image = CowDiskImage(child=RawDiskImage(read_only=True),
146 read_only=False)
147
148 def childImage(self, ci):
149 self.image.child.image_file = ci
150
151 self = SparcSystem()
152 if not mdesc:
153 # generic system
154 mdesc = SysConfig()
155 self.readfile = mdesc.script()
156 self.iobus = IOXBar()
157 self.membus = MemBus()
158 self.bridge = Bridge(delay='50ns')
159 self.t1000 = T1000()
160 self.t1000.attachOnChipIO(self.membus)
161 self.t1000.attachIO(self.iobus)
162 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
163 AddrRange(Addr('2GB'), size ='256MB')]
164 self.bridge.master = self.iobus.slave
165 self.bridge.slave = self.membus.master
166 self.rom.port = self.membus.master
167 self.nvram.port = self.membus.master
168 self.hypervisor_desc.port = self.membus.master
169 self.partition_desc.port = self.membus.master
170 self.intrctrl = IntrControl()
171 self.disk0 = CowMmDisk()
172 self.disk0.childImage(mdesc.disk())
173 self.disk0.pio = self.iobus.master
174
175 # The puart0 and hvuart are placed on the IO bus, so create ranges
176 # for them. The remaining IO range is rather fragmented, so poke
177 # holes for the iob and partition descriptors etc.
178 self.bridge.ranges = \
179 [
180 AddrRange(self.t1000.puart0.pio_addr,
181 self.t1000.puart0.pio_addr + uart_pio_size - 1),
182 AddrRange(self.disk0.pio_addr,
183 self.t1000.fake_jbi.pio_addr +
184 self.t1000.fake_jbi.pio_size - 1),
185 AddrRange(self.t1000.fake_clk.pio_addr,
186 iob_man_addr - 1),
187 AddrRange(self.t1000.fake_l2_1.pio_addr,
188 self.t1000.fake_ssi.pio_addr +
189 self.t1000.fake_ssi.pio_size - 1),
190 AddrRange(self.t1000.hvuart.pio_addr,
191 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
192 ]
193 self.reset_bin = binary('reset_new.bin')
194 self.hypervisor_bin = binary('q_new.bin')
195 self.openboot_bin = binary('openboot_new.bin')
196 self.nvram_bin = binary('nvram1')
197 self.hypervisor_desc_bin = binary('1up-hv.bin')
198 self.partition_desc_bin = binary('1up-md.bin')
199
200 self.system_port = self.membus.slave
201
202 return self
203
204def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
205 dtb_filename=None, bare_metal=False, cmdline=None,
206 external_memory="", ruby=False):
207 assert machine_type
208
209 default_dtbs = {
210 "RealViewEB": None,
211 "RealViewPBX": None,
212 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus,
213 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
214 }
215
216 default_kernels = {
217 "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8",
218 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8",
219 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5",
220 "VExpress_EMM64": "vmlinux.aarch64.20140821",
221 }
222
223 pci_devices = []
224
225 if bare_metal:
226 self = ArmSystem()
227 else:
228 self = LinuxArmSystem()
229
230 if not mdesc:
231 # generic system
232 mdesc = SysConfig()
233
234 self.readfile = mdesc.script()
235 self.iobus = IOXBar()
236 if not ruby:
237 self.bridge = Bridge(delay='50ns')
238 self.bridge.master = self.iobus.slave
239 self.membus = MemBus()
240 self.membus.badaddr_responder.warn_access = "warn"
241 self.bridge.slave = self.membus.master
242
243 self.mem_mode = mem_mode
244
245 platform_class = PlatformConfig.get(machine_type)
246 # Resolve the real platform name, the original machine_type
247 # variable might have been an alias.
248 machine_type = platform_class.__name__
249 self.realview = platform_class()
250
251 if not dtb_filename and not bare_metal:
252 try:
253 dtb_filename = default_dtbs[machine_type]
254 except KeyError:
255 fatal("No DTB specified and no default DTB known for '%s'" % \
256 machine_type)
257
258 if isinstance(self.realview, VExpress_EMM64):
259 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
260 print "Selected 64-bit ARM architecture, updating default disk image..."
261 mdesc.diskname = 'linaro-minimal-aarch64.img'
262
263
264 # Attach any PCI devices this platform supports
265 self.realview.attachPciDevices()
266
267 self.cf0 = CowIdeDisk(driveID='master')
268 self.cf0.childImage(mdesc.disk())
269 # Old platforms have a built-in IDE or CF controller. Default to
270 # the IDE controller if both exist. New platforms expect the
271 # storage controller to be added from the config script.
272 if hasattr(self.realview, "ide"):
273 self.realview.ide.disks = [self.cf0]
274 elif hasattr(self.realview, "cf_ctrl"):
275 self.realview.cf_ctrl.disks = [self.cf0]
276 else:
277 self.pci_ide = IdeController(disks=[self.cf0])
278 pci_devices.append(self.pci_ide)
279
280 self.mem_ranges = []
281 size_remain = long(Addr(mdesc.mem()))
282 for region in self.realview._mem_regions:
283 if size_remain > long(region[1]):
284 self.mem_ranges.append(AddrRange(region[0], size=region[1]))
285 size_remain = size_remain - long(region[1])
286 else:
287 self.mem_ranges.append(AddrRange(region[0], size=size_remain))
288 size_remain = 0
289 break
290 warn("Memory size specified spans more than one region. Creating" \
291 " another memory controller for that range.")
292
293 if size_remain > 0:
294 fatal("The currently selected ARM platforms doesn't support" \
295 " the amount of DRAM you've selected. Please try" \
296 " another platform")
297
298 if bare_metal:
299 # EOT character on UART will end the simulation
300 self.realview.uart.end_on_eot = True
301 else:
302 if machine_type in default_kernels:
303 self.kernel = binary(default_kernels[machine_type])
304
305 if dtb_filename:
306 self.dtb_filename = binary(dtb_filename)
307
308 self.machine_type = machine_type if machine_type in ArmMachineType.map \
309 else "DTOnly"
310
311 # Ensure that writes to the UART actually go out early in the boot
312 if not cmdline:
313 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
314 'lpj=19988480 norandmaps rw loglevel=8 ' + \
315 'mem=%(mem)s root=%(rootdev)s'
316
317 # When using external memory, gem5 writes the boot loader to nvmem
318 # and then SST will read from it, but SST can only get to nvmem from
319 # iobus, as gem5's membus is only used for initialization and
320 # SST doesn't use it. Attaching nvmem to iobus solves this issue.
321 # During initialization, system_port -> membus -> iobus -> nvmem.
322 if external_memory or ruby:
323 self.realview.setupBootLoader(self.iobus, self, binary)
324 else:
325 self.realview.setupBootLoader(self.membus, self, binary)
326 self.gic_cpu_addr = self.realview.gic.cpu_addr
327 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
328
329 # This check is for users who have previously put 'android' in
330 # the disk image filename to tell the config scripts to
331 # prepare the kernel with android-specific boot options. That
332 # behavior has been replaced with a more explicit option per
333 # the error message below. The disk can have any name now and
334 # doesn't need to include 'android' substring.
335 if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
336 if 'android' not in mdesc.os_type():
337 fatal("It looks like you are trying to boot an Android " \
338 "platform. To boot Android, you must specify " \
339 "--os-type with an appropriate Android release on " \
340 "the command line.")
341
342 # android-specific tweaks
343 if 'android' in mdesc.os_type():
344 # generic tweaks
345 cmdline += " init=/init"
346
347 # release-specific tweaks
348 if 'kitkat' in mdesc.os_type():
349 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
350 "android.bootanim=0"
351
352 self.boot_osflags = fillInCmdline(mdesc, cmdline)
353
354 if external_memory:
355 # I/O traffic enters iobus
356 self.external_io = ExternalMaster(port_data="external_io",
357 port_type=external_memory)
358 self.external_io.port = self.iobus.slave
359
360 # Ensure iocache only receives traffic destined for (actual) memory.
361 self.iocache = ExternalSlave(port_data="iocache",
362 port_type=external_memory,
363 addr_ranges=self.mem_ranges)
364 self.iocache.port = self.iobus.master
365
366 # Let system_port get to nvmem and nothing else.
367 self.bridge.ranges = [self.realview.nvmem.range]
368
369 self.realview.attachOnChipIO(self.iobus)
370 # Attach off-chip devices
371 self.realview.attachIO(self.iobus)
372 elif ruby:
373 self._dma_ports = [ ]
374 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
375 # Force Ruby to treat the boot ROM as an IO device.
376 self.realview.nvmem.in_addr_map = False
377 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
378 else:
379 self.realview.attachOnChipIO(self.membus, self.bridge)
380 # Attach off-chip devices
381 self.realview.attachIO(self.iobus)
382
383 for dev_id, dev in enumerate(pci_devices):
384 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
385 self.realview.attachPciDevice(
386 dev, self.iobus,
387 dma_ports=self._dma_ports if ruby else None)
388
389 self.intrctrl = IntrControl()
390 self.terminal = Terminal()
391 self.vncserver = VncServer()
392
393 if not ruby:
394 self.system_port = self.membus.slave
395
396 if ruby:
397 fatal("You're trying to use Ruby on ARM, which is not working " \
398 "properly yet. If you want to test it anyway, you " \
399 "need to remove this fatal error from FSConfig.py.")
400
401 return self
402
403
404def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
405 class BaseMalta(Malta):
406 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
407 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
408 pci_func=0, pci_dev=0, pci_bus=0)
409
410 self = LinuxMipsSystem()
411 if not mdesc:
412 # generic system
413 mdesc = SysConfig()
414 self.readfile = mdesc.script()
415 self.iobus = IOXBar()
416 self.membus = MemBus()
417 self.bridge = Bridge(delay='50ns')
418 self.mem_ranges = [AddrRange('1GB')]
419 self.bridge.master = self.iobus.slave
420 self.bridge.slave = self.membus.master
421 self.disk0 = CowIdeDisk(driveID='master')
422 self.disk2 = CowIdeDisk(driveID='master')
423 self.disk0.childImage(mdesc.disk())
424 self.disk2.childImage(disk('linux-bigswap2.img'))
425 self.malta = BaseMalta()
426 self.malta.attachIO(self.iobus)
427 self.malta.ide.pio = self.iobus.master
428 self.malta.ide.dma = self.iobus.slave
429 self.malta.ethernet.pio = self.iobus.master
430 self.malta.ethernet.dma = self.iobus.slave
431 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
432 read_only = True))
433 self.intrctrl = IntrControl()
434 self.mem_mode = mem_mode
435 self.terminal = Terminal()
436 self.kernel = binary('mips/vmlinux')
437 self.console = binary('mips/console')
438 if not cmdline:
439 cmdline = 'root=/dev/hda1 console=ttyS0'
440 self.boot_osflags = fillInCmdline(mdesc, cmdline)
441
442 self.system_port = self.membus.slave
443
444 return self
445
446def x86IOAddress(port):
447 IO_address_space_base = 0x8000000000000000
448 return IO_address_space_base + port
449
450def connectX86ClassicSystem(x86_sys, numCPUs):
451 # Constants similar to x86_traits.hh
452 IO_address_space_base = 0x8000000000000000
453 pci_config_address_space_base = 0xc000000000000000
454 interrupts_address_space_base = 0xa000000000000000
455 APIC_range_size = 1 << 12;
456
457 x86_sys.membus = MemBus()
458
459 # North Bridge
460 x86_sys.iobus = IOXBar()
461 x86_sys.bridge = Bridge(delay='50ns')
462 x86_sys.bridge.master = x86_sys.iobus.slave
463 x86_sys.bridge.slave = x86_sys.membus.master
464 # Allow the bridge to pass through:
465 # 1) kernel configured PCI device memory map address: address range
466 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
467 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
468 # 3) everything in the IO address range up to the local APIC, and
469 # 4) then the entire PCI address space and beyond.
470 x86_sys.bridge.ranges = \
471 [
472 AddrRange(0xC0000000, 0xFFFF0000),
473 AddrRange(IO_address_space_base,
474 interrupts_address_space_base - 1),
475 AddrRange(pci_config_address_space_base,
476 Addr.max)
477 ]
478
479 # Create a bridge from the IO bus to the memory bus to allow access to
480 # the local APIC (two pages)
481 x86_sys.apicbridge = Bridge(delay='50ns')
482 x86_sys.apicbridge.slave = x86_sys.iobus.master
483 x86_sys.apicbridge.master = x86_sys.membus.slave
484 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
485 interrupts_address_space_base +
486 numCPUs * APIC_range_size
487 - 1)]
488
489 # connect the io bus
490 x86_sys.pc.attachIO(x86_sys.iobus)
491
492 x86_sys.system_port = x86_sys.membus.slave
493
494def connectX86RubySystem(x86_sys):
495 # North Bridge
496 x86_sys.iobus = IOXBar()
497
498 # add the ide to the list of dma devices that later need to attach to
499 # dma controllers
500 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
501 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
502
503
504def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
505 if self == None:
506 self = X86System()
507
508 if not mdesc:
509 # generic system
510 mdesc = SysConfig()
511 self.readfile = mdesc.script()
512
513 self.mem_mode = mem_mode
514
515 # Physical memory
516 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
517 # for various devices. Hence, if the physical memory size is greater than
518 # 3GB, we need to split it into two parts.
519 excess_mem_size = \
520 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
521 if excess_mem_size <= 0:
522 self.mem_ranges = [AddrRange(mdesc.mem())]
523 else:
524 warn("Physical memory size specified is %s which is greater than " \
525 "3GB. Twice the number of memory controllers would be " \
526 "created." % (mdesc.mem()))
527
528 self.mem_ranges = [AddrRange('3GB'),
529 AddrRange(Addr('4GB'), size = excess_mem_size)]
530
531 # Platform
532 self.pc = Pc()
533
534 # Create and connect the busses required by each memory system
535 if Ruby:
536 connectX86RubySystem(self)
537 else:
538 connectX86ClassicSystem(self, numCPUs)
539
540 self.intrctrl = IntrControl()
541
542 # Disks
543 disk0 = CowIdeDisk(driveID='master')
544 disk2 = CowIdeDisk(driveID='master')
545 disk0.childImage(mdesc.disk())
546 disk2.childImage(disk('linux-bigswap2.img'))
547 self.pc.south_bridge.ide.disks = [disk0, disk2]
548
549 # Add in a Bios information structure.
550 structures = [X86SMBiosBiosInformation()]
551 self.smbios_table.structures = structures
552
553 # Set up the Intel MP table
554 base_entries = []
555 ext_entries = []
556 for i in xrange(numCPUs):
557 bp = X86IntelMPProcessor(
558 local_apic_id = i,
559 local_apic_version = 0x14,
560 enable = True,
561 bootstrap = (i == 0))
562 base_entries.append(bp)
563 io_apic = X86IntelMPIOAPIC(
564 id = numCPUs,
565 version = 0x11,
566 enable = True,
567 address = 0xfec00000)
568 self.pc.south_bridge.io_apic.apic_id = io_apic.id
569 base_entries.append(io_apic)
570 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
571 # but linux kernel cannot config PCI device if it was not connected to PCI bus,
572 # so we fix PCI bus id to 0, and ISA bus id to 1.
573 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
574 base_entries.append(pci_bus)
575 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
576 base_entries.append(isa_bus)
577 connect_busses = X86IntelMPBusHierarchy(bus_id=1,
578 subtractive_decode=True, parent_bus=0)
579 ext_entries.append(connect_busses)
580 pci_dev4_inta = X86IntelMPIOIntAssignment(
581 interrupt_type = 'INT',
582 polarity = 'ConformPolarity',
583 trigger = 'ConformTrigger',
584 source_bus_id = 0,
585 source_bus_irq = 0 + (4 << 2),
586 dest_io_apic_id = io_apic.id,
587 dest_io_apic_intin = 16)
588 base_entries.append(pci_dev4_inta)
589 def assignISAInt(irq, apicPin):
590 assign_8259_to_apic = X86IntelMPIOIntAssignment(
591 interrupt_type = 'ExtInt',
592 polarity = 'ConformPolarity',
593 trigger = 'ConformTrigger',
594 source_bus_id = 1,
595 source_bus_irq = irq,
596 dest_io_apic_id = io_apic.id,
597 dest_io_apic_intin = 0)
598 base_entries.append(assign_8259_to_apic)
599 assign_to_apic = X86IntelMPIOIntAssignment(
600 interrupt_type = 'INT',
601 polarity = 'ConformPolarity',
602 trigger = 'ConformTrigger',
603 source_bus_id = 1,
604 source_bus_irq = irq,
605 dest_io_apic_id = io_apic.id,
606 dest_io_apic_intin = apicPin)
607 base_entries.append(assign_to_apic)
608 assignISAInt(0, 2)
609 assignISAInt(1, 1)
610 for i in range(3, 15):
611 assignISAInt(i, i)
612 self.intel_mp_table.base_entries = base_entries
613 self.intel_mp_table.ext_entries = ext_entries
614
615def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
616 cmdline=None):
617 self = LinuxX86System()
618
619 # Build up the x86 system and then specialize it for Linux
620 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
621
622 # We assume below that there's at least 1MB of memory. We'll require 2
623 # just to avoid corner cases.
624 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
625 assert(phys_mem_size >= 0x200000)
626 assert(len(self.mem_ranges) <= 2)
627
628 entries = \
629 [
630 # Mark the first megabyte of memory as reserved
631 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
632 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
633 # Mark the rest of physical memory as available
634 X86E820Entry(addr = 0x100000,
635 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
636 range_type = 1),
637 ]
638
639 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
640 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
641 # specific range can pass though bridge to iobus.
642 if len(self.mem_ranges) == 1:
643 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
644 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
645 range_type=2))
646
647 # Reserve the last 16kB of the 32-bit address space for the m5op interface
648 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
649
650 # In case the physical memory is greater than 3GB, we split it into two
651 # parts and add a separate e820 entry for the second part. This entry
652 # starts at 0x100000000, which is the first address after the space
653 # reserved for devices.
654 if len(self.mem_ranges) == 2:
655 entries.append(X86E820Entry(addr = 0x100000000,
656 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
657
658 self.e820_table.entries = entries
659
660 # Command line
661 if not cmdline:
662 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
663 self.boot_osflags = fillInCmdline(mdesc, cmdline)
664 self.kernel = binary('x86_64-vmlinux-2.6.22.9')
665 return self
666
667
668def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
669 self = Root(full_system = full_system)
670 self.testsys = testSystem
671 self.drivesys = driveSystem
672 self.etherlink = EtherLink()
673
674 if hasattr(testSystem, 'realview'):
675 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
676 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
677 elif hasattr(testSystem, 'tsunami'):
678 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
679 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
680 else:
681 fatal("Don't know how to connect these system together")
682
683 if dumpfile:
684 self.etherdump = EtherDump(file=dumpfile)
685 self.etherlink.dump = Parent.etherdump
686
687 return self
688
689
690def makeDistRoot(testSystem,
691 rank,
692 size,
693 server_name,
694 server_port,
695 sync_repeat,
696 sync_start,
697 linkspeed,
698 linkdelay,
699 dumpfile):
700 self = Root(full_system = True)
701 self.testsys = testSystem
702
703 self.etherlink = DistEtherLink(speed = linkspeed,
704 delay = linkdelay,
705 dist_rank = rank,
706 dist_size = size,
707 server_name = server_name,
708 server_port = server_port,
709 sync_start = sync_start,
710 sync_repeat = sync_repeat)
711
712 if hasattr(testSystem, 'realview'):
713 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
714 elif hasattr(testSystem, 'tsunami'):
715 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
716 else:
717 fatal("Don't know how to connect DistEtherLink to this system")
718
719 if dumpfile:
720 self.etherdump = EtherDump(file=dumpfile)
721 self.etherlink.dump = Parent.etherdump
722
723 return self
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