1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46class CowIdeDisk(IdeDisk):
47 image = CowDiskImage(child=RawDiskImage(read_only=True),
48 read_only=False)
49
50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
59
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70
71 self.tsunami = BaseTsunami()
72
73 # Create the io bus to connect all device ports
74 self.iobus = NoncoherentBus()
75 self.tsunami.attachIO(self.iobus)
76
77 self.tsunami.ide.pio = self.iobus.master
78 self.tsunami.ide.config = self.iobus.master
79
80 self.tsunami.ethernet.pio = self.iobus.master
81 self.tsunami.ethernet.config = self.iobus.master
82
83 if ruby:
84 # Store the dma devices for later connection to dma ruby ports.
85 # Append an underscore to dma_ports to avoid the SimObjectVector check.
86 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
87 else:
88 self.membus = MemBus()
89
90 # By default the bridge responds to all addresses above the I/O
91 # base address (including the PCI config space)
92 IO_address_space_base = 0x80000000000
93 self.bridge = Bridge(delay='50ns',
94 ranges = [AddrRange(IO_address_space_base, Addr.max)])
95 self.bridge.master = self.iobus.slave
96 self.bridge.slave = self.membus.master
97
98 self.tsunami.ide.dma = self.iobus.slave
99 self.tsunami.ethernet.dma = self.iobus.slave
100
101 self.system_port = self.membus.slave
102
103 self.mem_ranges = [AddrRange(mdesc.mem())]
104 self.disk0 = CowIdeDisk(driveID='master')
105 self.disk2 = CowIdeDisk(driveID='master')
106 self.disk0.childImage(mdesc.disk())
107 self.disk2.childImage(disk('linux-bigswap2.img'))
108 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
109 read_only = True))
110 self.intrctrl = IntrControl()
111 self.mem_mode = mem_mode
112 self.terminal = Terminal()
113 self.kernel = binary('vmlinux')
114 self.pal = binary('ts_osfpal')
115 self.console = binary('console')
116 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
117
118 return self
119
120def makeSparcSystem(mem_mode, mdesc = None):
121 # Constants from iob.cc and uart8250.cc
122 iob_man_addr = 0x9800000000
123 uart_pio_size = 8
124
125 class CowMmDisk(MmDisk):
126 image = CowDiskImage(child=RawDiskImage(read_only=True),
127 read_only=False)
128
129 def childImage(self, ci):
130 self.image.child.image_file = ci
131
132 self = SparcSystem()
133 if not mdesc:
134 # generic system
135 mdesc = SysConfig()
136 self.readfile = mdesc.script()
137 self.iobus = NoncoherentBus()
138 self.membus = MemBus()
139 self.bridge = Bridge(delay='50ns')
140 self.t1000 = T1000()
141 self.t1000.attachOnChipIO(self.membus)
142 self.t1000.attachIO(self.iobus)
143 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
144 AddrRange(Addr('2GB'), size ='256MB')]
145 self.bridge.master = self.iobus.slave
146 self.bridge.slave = self.membus.master
147 self.rom.port = self.membus.master
148 self.nvram.port = self.membus.master
149 self.hypervisor_desc.port = self.membus.master
150 self.partition_desc.port = self.membus.master
151 self.intrctrl = IntrControl()
152 self.disk0 = CowMmDisk()
153 self.disk0.childImage(disk('disk.s10hw2'))
154 self.disk0.pio = self.iobus.master
155
156 # The puart0 and hvuart are placed on the IO bus, so create ranges
157 # for them. The remaining IO range is rather fragmented, so poke
158 # holes for the iob and partition descriptors etc.
159 self.bridge.ranges = \
160 [
161 AddrRange(self.t1000.puart0.pio_addr,
162 self.t1000.puart0.pio_addr + uart_pio_size - 1),
163 AddrRange(self.disk0.pio_addr,
164 self.t1000.fake_jbi.pio_addr +
165 self.t1000.fake_jbi.pio_size - 1),
166 AddrRange(self.t1000.fake_clk.pio_addr,
167 iob_man_addr - 1),
168 AddrRange(self.t1000.fake_l2_1.pio_addr,
169 self.t1000.fake_ssi.pio_addr +
170 self.t1000.fake_ssi.pio_size - 1),
171 AddrRange(self.t1000.hvuart.pio_addr,
172 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
173 ]
174 self.reset_bin = binary('reset_new.bin')
175 self.hypervisor_bin = binary('q_new.bin')
176 self.openboot_bin = binary('openboot_new.bin')
177 self.nvram_bin = binary('nvram1')
178 self.hypervisor_desc_bin = binary('1up-hv.bin')
179 self.partition_desc_bin = binary('1up-md.bin')
180
181 self.system_port = self.membus.slave
182
183 return self
184
185def makeArmSystem(mem_mode, machine_type, mdesc = None,
186 dtb_filename = None, bare_metal=False):
187 assert machine_type
188
189 if bare_metal:
190 self = ArmSystem()
191 else:
192 self = LinuxArmSystem()
193
194 if not mdesc:
195 # generic system
196 mdesc = SysConfig()
197
198 self.readfile = mdesc.script()
199 self.iobus = NoncoherentBus()
200 self.membus = MemBus()
201 self.membus.badaddr_responder.warn_access = "warn"
202 self.bridge = Bridge(delay='50ns')
203 self.bridge.master = self.iobus.slave
204 self.bridge.slave = self.membus.master
205
206 self.mem_mode = mem_mode
207
208 if machine_type == "RealView_PBX":
209 self.realview = RealViewPBX()
210 elif machine_type == "RealView_EB":
211 self.realview = RealViewEB()
212 elif machine_type == "VExpress_ELT":
213 self.realview = VExpress_ELT()
214 elif machine_type == "VExpress_EMM":
215 self.realview = VExpress_EMM()
216 elif machine_type == "VExpress_EMM64":
217 self.realview = VExpress_EMM64()
218 else:
219 print "Unknown Machine Type"
220 sys.exit(1)
221
222 self.cf0 = CowIdeDisk(driveID='master')
223 self.cf0.childImage(mdesc.disk())
224
225 # Attach any PCI devices this platform supports
226 self.realview.attachPciDevices()
227 # default to an IDE controller rather than a CF one
228 try:
229 self.realview.ide.disks = [self.cf0]
230 except:
231 self.realview.cf_ctrl.disks = [self.cf0]
232
233 if bare_metal:
234 # EOT character on UART will end the simulation
235 self.realview.uart.end_on_eot = True
236 self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
237 size = mdesc.mem())]
238 else:
239 if machine_type == "VExpress_EMM64":
240 self.kernel = binary('vmlinux-3.16-aarch64-vexpress-emm64-pcie')
241 elif machine_type == "VExpress_EMM":
242 self.kernel = binary('vmlinux-3.3-arm-vexpress-emm-pcie')
243 else:
244 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
245
246 if dtb_filename:
247 self.dtb_filename = binary(dtb_filename)
248 self.machine_type = machine_type
| 1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46class CowIdeDisk(IdeDisk):
47 image = CowDiskImage(child=RawDiskImage(read_only=True),
48 read_only=False)
49
50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
59
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70
71 self.tsunami = BaseTsunami()
72
73 # Create the io bus to connect all device ports
74 self.iobus = NoncoherentBus()
75 self.tsunami.attachIO(self.iobus)
76
77 self.tsunami.ide.pio = self.iobus.master
78 self.tsunami.ide.config = self.iobus.master
79
80 self.tsunami.ethernet.pio = self.iobus.master
81 self.tsunami.ethernet.config = self.iobus.master
82
83 if ruby:
84 # Store the dma devices for later connection to dma ruby ports.
85 # Append an underscore to dma_ports to avoid the SimObjectVector check.
86 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
87 else:
88 self.membus = MemBus()
89
90 # By default the bridge responds to all addresses above the I/O
91 # base address (including the PCI config space)
92 IO_address_space_base = 0x80000000000
93 self.bridge = Bridge(delay='50ns',
94 ranges = [AddrRange(IO_address_space_base, Addr.max)])
95 self.bridge.master = self.iobus.slave
96 self.bridge.slave = self.membus.master
97
98 self.tsunami.ide.dma = self.iobus.slave
99 self.tsunami.ethernet.dma = self.iobus.slave
100
101 self.system_port = self.membus.slave
102
103 self.mem_ranges = [AddrRange(mdesc.mem())]
104 self.disk0 = CowIdeDisk(driveID='master')
105 self.disk2 = CowIdeDisk(driveID='master')
106 self.disk0.childImage(mdesc.disk())
107 self.disk2.childImage(disk('linux-bigswap2.img'))
108 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
109 read_only = True))
110 self.intrctrl = IntrControl()
111 self.mem_mode = mem_mode
112 self.terminal = Terminal()
113 self.kernel = binary('vmlinux')
114 self.pal = binary('ts_osfpal')
115 self.console = binary('console')
116 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
117
118 return self
119
120def makeSparcSystem(mem_mode, mdesc = None):
121 # Constants from iob.cc and uart8250.cc
122 iob_man_addr = 0x9800000000
123 uart_pio_size = 8
124
125 class CowMmDisk(MmDisk):
126 image = CowDiskImage(child=RawDiskImage(read_only=True),
127 read_only=False)
128
129 def childImage(self, ci):
130 self.image.child.image_file = ci
131
132 self = SparcSystem()
133 if not mdesc:
134 # generic system
135 mdesc = SysConfig()
136 self.readfile = mdesc.script()
137 self.iobus = NoncoherentBus()
138 self.membus = MemBus()
139 self.bridge = Bridge(delay='50ns')
140 self.t1000 = T1000()
141 self.t1000.attachOnChipIO(self.membus)
142 self.t1000.attachIO(self.iobus)
143 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
144 AddrRange(Addr('2GB'), size ='256MB')]
145 self.bridge.master = self.iobus.slave
146 self.bridge.slave = self.membus.master
147 self.rom.port = self.membus.master
148 self.nvram.port = self.membus.master
149 self.hypervisor_desc.port = self.membus.master
150 self.partition_desc.port = self.membus.master
151 self.intrctrl = IntrControl()
152 self.disk0 = CowMmDisk()
153 self.disk0.childImage(disk('disk.s10hw2'))
154 self.disk0.pio = self.iobus.master
155
156 # The puart0 and hvuart are placed on the IO bus, so create ranges
157 # for them. The remaining IO range is rather fragmented, so poke
158 # holes for the iob and partition descriptors etc.
159 self.bridge.ranges = \
160 [
161 AddrRange(self.t1000.puart0.pio_addr,
162 self.t1000.puart0.pio_addr + uart_pio_size - 1),
163 AddrRange(self.disk0.pio_addr,
164 self.t1000.fake_jbi.pio_addr +
165 self.t1000.fake_jbi.pio_size - 1),
166 AddrRange(self.t1000.fake_clk.pio_addr,
167 iob_man_addr - 1),
168 AddrRange(self.t1000.fake_l2_1.pio_addr,
169 self.t1000.fake_ssi.pio_addr +
170 self.t1000.fake_ssi.pio_size - 1),
171 AddrRange(self.t1000.hvuart.pio_addr,
172 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
173 ]
174 self.reset_bin = binary('reset_new.bin')
175 self.hypervisor_bin = binary('q_new.bin')
176 self.openboot_bin = binary('openboot_new.bin')
177 self.nvram_bin = binary('nvram1')
178 self.hypervisor_desc_bin = binary('1up-hv.bin')
179 self.partition_desc_bin = binary('1up-md.bin')
180
181 self.system_port = self.membus.slave
182
183 return self
184
185def makeArmSystem(mem_mode, machine_type, mdesc = None,
186 dtb_filename = None, bare_metal=False):
187 assert machine_type
188
189 if bare_metal:
190 self = ArmSystem()
191 else:
192 self = LinuxArmSystem()
193
194 if not mdesc:
195 # generic system
196 mdesc = SysConfig()
197
198 self.readfile = mdesc.script()
199 self.iobus = NoncoherentBus()
200 self.membus = MemBus()
201 self.membus.badaddr_responder.warn_access = "warn"
202 self.bridge = Bridge(delay='50ns')
203 self.bridge.master = self.iobus.slave
204 self.bridge.slave = self.membus.master
205
206 self.mem_mode = mem_mode
207
208 if machine_type == "RealView_PBX":
209 self.realview = RealViewPBX()
210 elif machine_type == "RealView_EB":
211 self.realview = RealViewEB()
212 elif machine_type == "VExpress_ELT":
213 self.realview = VExpress_ELT()
214 elif machine_type == "VExpress_EMM":
215 self.realview = VExpress_EMM()
216 elif machine_type == "VExpress_EMM64":
217 self.realview = VExpress_EMM64()
218 else:
219 print "Unknown Machine Type"
220 sys.exit(1)
221
222 self.cf0 = CowIdeDisk(driveID='master')
223 self.cf0.childImage(mdesc.disk())
224
225 # Attach any PCI devices this platform supports
226 self.realview.attachPciDevices()
227 # default to an IDE controller rather than a CF one
228 try:
229 self.realview.ide.disks = [self.cf0]
230 except:
231 self.realview.cf_ctrl.disks = [self.cf0]
232
233 if bare_metal:
234 # EOT character on UART will end the simulation
235 self.realview.uart.end_on_eot = True
236 self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
237 size = mdesc.mem())]
238 else:
239 if machine_type == "VExpress_EMM64":
240 self.kernel = binary('vmlinux-3.16-aarch64-vexpress-emm64-pcie')
241 elif machine_type == "VExpress_EMM":
242 self.kernel = binary('vmlinux-3.3-arm-vexpress-emm-pcie')
243 else:
244 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
245
246 if dtb_filename:
247 self.dtb_filename = binary(dtb_filename)
248 self.machine_type = machine_type
|
262 self.realview.setupBootLoader(self.membus, self, binary)
263 self.gic_cpu_addr = self.realview.gic.cpu_addr
264 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
265
266 if mdesc.disk().lower().count('android'):
267 boot_flags += " init=/init "
268 self.boot_osflags = boot_flags
269 self.realview.attachOnChipIO(self.membus, self.bridge)
270 self.realview.attachIO(self.iobus)
271 self.intrctrl = IntrControl()
272 self.terminal = Terminal()
273 self.vncserver = VncServer()
274
275 self.system_port = self.membus.slave
276
277 return self
278
279
280def makeLinuxMipsSystem(mem_mode, mdesc = None):
281 class BaseMalta(Malta):
282 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
283 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
284 pci_func=0, pci_dev=0, pci_bus=0)
285
286 self = LinuxMipsSystem()
287 if not mdesc:
288 # generic system
289 mdesc = SysConfig()
290 self.readfile = mdesc.script()
291 self.iobus = NoncoherentBus()
292 self.membus = MemBus()
293 self.bridge = Bridge(delay='50ns')
294 self.mem_ranges = [AddrRange('1GB')]
295 self.bridge.master = self.iobus.slave
296 self.bridge.slave = self.membus.master
297 self.disk0 = CowIdeDisk(driveID='master')
298 self.disk2 = CowIdeDisk(driveID='master')
299 self.disk0.childImage(mdesc.disk())
300 self.disk2.childImage(disk('linux-bigswap2.img'))
301 self.malta = BaseMalta()
302 self.malta.attachIO(self.iobus)
303 self.malta.ide.pio = self.iobus.master
304 self.malta.ide.config = self.iobus.master
305 self.malta.ide.dma = self.iobus.slave
306 self.malta.ethernet.pio = self.iobus.master
307 self.malta.ethernet.config = self.iobus.master
308 self.malta.ethernet.dma = self.iobus.slave
309 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
310 read_only = True))
311 self.intrctrl = IntrControl()
312 self.mem_mode = mem_mode
313 self.terminal = Terminal()
314 self.kernel = binary('mips/vmlinux')
315 self.console = binary('mips/console')
316 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
317
318 self.system_port = self.membus.slave
319
320 return self
321
322def x86IOAddress(port):
323 IO_address_space_base = 0x8000000000000000
324 return IO_address_space_base + port
325
326def connectX86ClassicSystem(x86_sys, numCPUs):
327 # Constants similar to x86_traits.hh
328 IO_address_space_base = 0x8000000000000000
329 pci_config_address_space_base = 0xc000000000000000
330 interrupts_address_space_base = 0xa000000000000000
331 APIC_range_size = 1 << 12;
332
333 x86_sys.membus = MemBus()
334
335 # North Bridge
336 x86_sys.iobus = NoncoherentBus()
337 x86_sys.bridge = Bridge(delay='50ns')
338 x86_sys.bridge.master = x86_sys.iobus.slave
339 x86_sys.bridge.slave = x86_sys.membus.master
340 # Allow the bridge to pass through the IO APIC (two pages),
341 # everything in the IO address range up to the local APIC, and
342 # then the entire PCI address space and beyond
343 x86_sys.bridge.ranges = \
344 [
345 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
346 x86_sys.pc.south_bridge.io_apic.pio_addr +
347 APIC_range_size - 1),
348 AddrRange(IO_address_space_base,
349 interrupts_address_space_base - 1),
350 AddrRange(pci_config_address_space_base,
351 Addr.max)
352 ]
353
354 # Create a bridge from the IO bus to the memory bus to allow access to
355 # the local APIC (two pages)
356 x86_sys.apicbridge = Bridge(delay='50ns')
357 x86_sys.apicbridge.slave = x86_sys.iobus.master
358 x86_sys.apicbridge.master = x86_sys.membus.slave
359 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
360 interrupts_address_space_base +
361 numCPUs * APIC_range_size
362 - 1)]
363
364 # connect the io bus
365 x86_sys.pc.attachIO(x86_sys.iobus)
366
367 x86_sys.system_port = x86_sys.membus.slave
368
369def connectX86RubySystem(x86_sys):
370 # North Bridge
371 x86_sys.iobus = NoncoherentBus()
372
373 # add the ide to the list of dma devices that later need to attach to
374 # dma controllers
375 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
376 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
377
378
379def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
380 Ruby = False):
381 if self == None:
382 self = X86System()
383
384 if not mdesc:
385 # generic system
386 mdesc = SysConfig()
387 self.readfile = mdesc.script()
388
389 self.mem_mode = mem_mode
390
391 # Physical memory
392 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
393 # for various devices. Hence, if the physical memory size is greater than
394 # 3GB, we need to split it into two parts.
395 excess_mem_size = \
396 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
397 if excess_mem_size <= 0:
398 self.mem_ranges = [AddrRange(mdesc.mem())]
399 else:
400 warn("Physical memory size specified is %s which is greater than " \
401 "3GB. Twice the number of memory controllers would be " \
402 "created." % (mdesc.mem()))
403
404 self.mem_ranges = [AddrRange('3GB'),
405 AddrRange(Addr('4GB'), size = excess_mem_size)]
406
407 # Platform
408 self.pc = Pc()
409
410 # Create and connect the busses required by each memory system
411 if Ruby:
412 connectX86RubySystem(self)
413 else:
414 connectX86ClassicSystem(self, numCPUs)
415
416 self.intrctrl = IntrControl()
417
418 # Disks
419 disk0 = CowIdeDisk(driveID='master')
420 disk2 = CowIdeDisk(driveID='master')
421 disk0.childImage(mdesc.disk())
422 disk2.childImage(disk('linux-bigswap2.img'))
423 self.pc.south_bridge.ide.disks = [disk0, disk2]
424
425 # Add in a Bios information structure.
426 structures = [X86SMBiosBiosInformation()]
427 self.smbios_table.structures = structures
428
429 # Set up the Intel MP table
430 base_entries = []
431 ext_entries = []
432 for i in xrange(numCPUs):
433 bp = X86IntelMPProcessor(
434 local_apic_id = i,
435 local_apic_version = 0x14,
436 enable = True,
437 bootstrap = (i == 0))
438 base_entries.append(bp)
439 io_apic = X86IntelMPIOAPIC(
440 id = numCPUs,
441 version = 0x11,
442 enable = True,
443 address = 0xfec00000)
444 self.pc.south_bridge.io_apic.apic_id = io_apic.id
445 base_entries.append(io_apic)
446 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
447 base_entries.append(isa_bus)
448 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
449 base_entries.append(pci_bus)
450 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
451 subtractive_decode=True, parent_bus=1)
452 ext_entries.append(connect_busses)
453 pci_dev4_inta = X86IntelMPIOIntAssignment(
454 interrupt_type = 'INT',
455 polarity = 'ConformPolarity',
456 trigger = 'ConformTrigger',
457 source_bus_id = 1,
458 source_bus_irq = 0 + (4 << 2),
459 dest_io_apic_id = io_apic.id,
460 dest_io_apic_intin = 16)
461 base_entries.append(pci_dev4_inta)
462 def assignISAInt(irq, apicPin):
463 assign_8259_to_apic = X86IntelMPIOIntAssignment(
464 interrupt_type = 'ExtInt',
465 polarity = 'ConformPolarity',
466 trigger = 'ConformTrigger',
467 source_bus_id = 0,
468 source_bus_irq = irq,
469 dest_io_apic_id = io_apic.id,
470 dest_io_apic_intin = 0)
471 base_entries.append(assign_8259_to_apic)
472 assign_to_apic = X86IntelMPIOIntAssignment(
473 interrupt_type = 'INT',
474 polarity = 'ConformPolarity',
475 trigger = 'ConformTrigger',
476 source_bus_id = 0,
477 source_bus_irq = irq,
478 dest_io_apic_id = io_apic.id,
479 dest_io_apic_intin = apicPin)
480 base_entries.append(assign_to_apic)
481 assignISAInt(0, 2)
482 assignISAInt(1, 1)
483 for i in range(3, 15):
484 assignISAInt(i, i)
485 self.intel_mp_table.base_entries = base_entries
486 self.intel_mp_table.ext_entries = ext_entries
487
488def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
489 Ruby = False):
490 self = LinuxX86System()
491
492 # Build up the x86 system and then specialize it for Linux
493 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
494
495 # We assume below that there's at least 1MB of memory. We'll require 2
496 # just to avoid corner cases.
497 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
498 assert(phys_mem_size >= 0x200000)
499 assert(len(self.mem_ranges) <= 2)
500
501 entries = \
502 [
503 # Mark the first megabyte of memory as reserved
504 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
505 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
506 # Mark the rest of physical memory as available
507 X86E820Entry(addr = 0x100000,
508 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
509 range_type = 1),
510 # Reserve the last 16kB of the 32-bit address space for the
511 # m5op interface
512 X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
513 ]
514
515 # In case the physical memory is greater than 3GB, we split it into two
516 # parts and add a separate e820 entry for the second part. This entry
517 # starts at 0x100000000, which is the first address after the space
518 # reserved for devices.
519 if len(self.mem_ranges) == 2:
520 entries.append(X86E820Entry(addr = 0x100000000,
521 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
522
523 self.e820_table.entries = entries
524
525 # Command line
526 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
527 'root=/dev/hda1'
528 self.kernel = binary('x86_64-vmlinux-2.6.22.9')
529 return self
530
531
532def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
533 self = Root(full_system = full_system)
534 self.testsys = testSystem
535 self.drivesys = driveSystem
536 self.etherlink = EtherLink()
537
538 if hasattr(testSystem, 'realview'):
539 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
540 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
541 elif hasattr(testSystem, 'tsunami'):
542 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
543 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
544 else:
545 fatal("Don't know how to connect these system together")
546
547 if dumpfile:
548 self.etherdump = EtherDump(file=dumpfile)
549 self.etherlink.dump = Parent.etherdump
550
551 return self
| 273 self.realview.setupBootLoader(self.membus, self, binary)
274 self.gic_cpu_addr = self.realview.gic.cpu_addr
275 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
276
277 if mdesc.disk().lower().count('android'):
278 boot_flags += " init=/init "
279 self.boot_osflags = boot_flags
280 self.realview.attachOnChipIO(self.membus, self.bridge)
281 self.realview.attachIO(self.iobus)
282 self.intrctrl = IntrControl()
283 self.terminal = Terminal()
284 self.vncserver = VncServer()
285
286 self.system_port = self.membus.slave
287
288 return self
289
290
291def makeLinuxMipsSystem(mem_mode, mdesc = None):
292 class BaseMalta(Malta):
293 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
294 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
295 pci_func=0, pci_dev=0, pci_bus=0)
296
297 self = LinuxMipsSystem()
298 if not mdesc:
299 # generic system
300 mdesc = SysConfig()
301 self.readfile = mdesc.script()
302 self.iobus = NoncoherentBus()
303 self.membus = MemBus()
304 self.bridge = Bridge(delay='50ns')
305 self.mem_ranges = [AddrRange('1GB')]
306 self.bridge.master = self.iobus.slave
307 self.bridge.slave = self.membus.master
308 self.disk0 = CowIdeDisk(driveID='master')
309 self.disk2 = CowIdeDisk(driveID='master')
310 self.disk0.childImage(mdesc.disk())
311 self.disk2.childImage(disk('linux-bigswap2.img'))
312 self.malta = BaseMalta()
313 self.malta.attachIO(self.iobus)
314 self.malta.ide.pio = self.iobus.master
315 self.malta.ide.config = self.iobus.master
316 self.malta.ide.dma = self.iobus.slave
317 self.malta.ethernet.pio = self.iobus.master
318 self.malta.ethernet.config = self.iobus.master
319 self.malta.ethernet.dma = self.iobus.slave
320 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
321 read_only = True))
322 self.intrctrl = IntrControl()
323 self.mem_mode = mem_mode
324 self.terminal = Terminal()
325 self.kernel = binary('mips/vmlinux')
326 self.console = binary('mips/console')
327 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
328
329 self.system_port = self.membus.slave
330
331 return self
332
333def x86IOAddress(port):
334 IO_address_space_base = 0x8000000000000000
335 return IO_address_space_base + port
336
337def connectX86ClassicSystem(x86_sys, numCPUs):
338 # Constants similar to x86_traits.hh
339 IO_address_space_base = 0x8000000000000000
340 pci_config_address_space_base = 0xc000000000000000
341 interrupts_address_space_base = 0xa000000000000000
342 APIC_range_size = 1 << 12;
343
344 x86_sys.membus = MemBus()
345
346 # North Bridge
347 x86_sys.iobus = NoncoherentBus()
348 x86_sys.bridge = Bridge(delay='50ns')
349 x86_sys.bridge.master = x86_sys.iobus.slave
350 x86_sys.bridge.slave = x86_sys.membus.master
351 # Allow the bridge to pass through the IO APIC (two pages),
352 # everything in the IO address range up to the local APIC, and
353 # then the entire PCI address space and beyond
354 x86_sys.bridge.ranges = \
355 [
356 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
357 x86_sys.pc.south_bridge.io_apic.pio_addr +
358 APIC_range_size - 1),
359 AddrRange(IO_address_space_base,
360 interrupts_address_space_base - 1),
361 AddrRange(pci_config_address_space_base,
362 Addr.max)
363 ]
364
365 # Create a bridge from the IO bus to the memory bus to allow access to
366 # the local APIC (two pages)
367 x86_sys.apicbridge = Bridge(delay='50ns')
368 x86_sys.apicbridge.slave = x86_sys.iobus.master
369 x86_sys.apicbridge.master = x86_sys.membus.slave
370 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
371 interrupts_address_space_base +
372 numCPUs * APIC_range_size
373 - 1)]
374
375 # connect the io bus
376 x86_sys.pc.attachIO(x86_sys.iobus)
377
378 x86_sys.system_port = x86_sys.membus.slave
379
380def connectX86RubySystem(x86_sys):
381 # North Bridge
382 x86_sys.iobus = NoncoherentBus()
383
384 # add the ide to the list of dma devices that later need to attach to
385 # dma controllers
386 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
387 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
388
389
390def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
391 Ruby = False):
392 if self == None:
393 self = X86System()
394
395 if not mdesc:
396 # generic system
397 mdesc = SysConfig()
398 self.readfile = mdesc.script()
399
400 self.mem_mode = mem_mode
401
402 # Physical memory
403 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
404 # for various devices. Hence, if the physical memory size is greater than
405 # 3GB, we need to split it into two parts.
406 excess_mem_size = \
407 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
408 if excess_mem_size <= 0:
409 self.mem_ranges = [AddrRange(mdesc.mem())]
410 else:
411 warn("Physical memory size specified is %s which is greater than " \
412 "3GB. Twice the number of memory controllers would be " \
413 "created." % (mdesc.mem()))
414
415 self.mem_ranges = [AddrRange('3GB'),
416 AddrRange(Addr('4GB'), size = excess_mem_size)]
417
418 # Platform
419 self.pc = Pc()
420
421 # Create and connect the busses required by each memory system
422 if Ruby:
423 connectX86RubySystem(self)
424 else:
425 connectX86ClassicSystem(self, numCPUs)
426
427 self.intrctrl = IntrControl()
428
429 # Disks
430 disk0 = CowIdeDisk(driveID='master')
431 disk2 = CowIdeDisk(driveID='master')
432 disk0.childImage(mdesc.disk())
433 disk2.childImage(disk('linux-bigswap2.img'))
434 self.pc.south_bridge.ide.disks = [disk0, disk2]
435
436 # Add in a Bios information structure.
437 structures = [X86SMBiosBiosInformation()]
438 self.smbios_table.structures = structures
439
440 # Set up the Intel MP table
441 base_entries = []
442 ext_entries = []
443 for i in xrange(numCPUs):
444 bp = X86IntelMPProcessor(
445 local_apic_id = i,
446 local_apic_version = 0x14,
447 enable = True,
448 bootstrap = (i == 0))
449 base_entries.append(bp)
450 io_apic = X86IntelMPIOAPIC(
451 id = numCPUs,
452 version = 0x11,
453 enable = True,
454 address = 0xfec00000)
455 self.pc.south_bridge.io_apic.apic_id = io_apic.id
456 base_entries.append(io_apic)
457 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
458 base_entries.append(isa_bus)
459 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
460 base_entries.append(pci_bus)
461 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
462 subtractive_decode=True, parent_bus=1)
463 ext_entries.append(connect_busses)
464 pci_dev4_inta = X86IntelMPIOIntAssignment(
465 interrupt_type = 'INT',
466 polarity = 'ConformPolarity',
467 trigger = 'ConformTrigger',
468 source_bus_id = 1,
469 source_bus_irq = 0 + (4 << 2),
470 dest_io_apic_id = io_apic.id,
471 dest_io_apic_intin = 16)
472 base_entries.append(pci_dev4_inta)
473 def assignISAInt(irq, apicPin):
474 assign_8259_to_apic = X86IntelMPIOIntAssignment(
475 interrupt_type = 'ExtInt',
476 polarity = 'ConformPolarity',
477 trigger = 'ConformTrigger',
478 source_bus_id = 0,
479 source_bus_irq = irq,
480 dest_io_apic_id = io_apic.id,
481 dest_io_apic_intin = 0)
482 base_entries.append(assign_8259_to_apic)
483 assign_to_apic = X86IntelMPIOIntAssignment(
484 interrupt_type = 'INT',
485 polarity = 'ConformPolarity',
486 trigger = 'ConformTrigger',
487 source_bus_id = 0,
488 source_bus_irq = irq,
489 dest_io_apic_id = io_apic.id,
490 dest_io_apic_intin = apicPin)
491 base_entries.append(assign_to_apic)
492 assignISAInt(0, 2)
493 assignISAInt(1, 1)
494 for i in range(3, 15):
495 assignISAInt(i, i)
496 self.intel_mp_table.base_entries = base_entries
497 self.intel_mp_table.ext_entries = ext_entries
498
499def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
500 Ruby = False):
501 self = LinuxX86System()
502
503 # Build up the x86 system and then specialize it for Linux
504 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
505
506 # We assume below that there's at least 1MB of memory. We'll require 2
507 # just to avoid corner cases.
508 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
509 assert(phys_mem_size >= 0x200000)
510 assert(len(self.mem_ranges) <= 2)
511
512 entries = \
513 [
514 # Mark the first megabyte of memory as reserved
515 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
516 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
517 # Mark the rest of physical memory as available
518 X86E820Entry(addr = 0x100000,
519 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
520 range_type = 1),
521 # Reserve the last 16kB of the 32-bit address space for the
522 # m5op interface
523 X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
524 ]
525
526 # In case the physical memory is greater than 3GB, we split it into two
527 # parts and add a separate e820 entry for the second part. This entry
528 # starts at 0x100000000, which is the first address after the space
529 # reserved for devices.
530 if len(self.mem_ranges) == 2:
531 entries.append(X86E820Entry(addr = 0x100000000,
532 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
533
534 self.e820_table.entries = entries
535
536 # Command line
537 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
538 'root=/dev/hda1'
539 self.kernel = binary('x86_64-vmlinux-2.6.22.9')
540 return self
541
542
543def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
544 self = Root(full_system = full_system)
545 self.testsys = testSystem
546 self.drivesys = driveSystem
547 self.etherlink = EtherLink()
548
549 if hasattr(testSystem, 'realview'):
550 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
551 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
552 elif hasattr(testSystem, 'tsunami'):
553 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
554 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
555 else:
556 fatal("Don't know how to connect these system together")
557
558 if dumpfile:
559 self.etherdump = EtherDump(file=dumpfile)
560 self.etherlink.dump = Parent.etherdump
561
562 return self
|