FSConfig.py (9707:1305bec2733f) | FSConfig.py (9826:014ff1fbff6d) |
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1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 41 unchanged lines hidden (view full) --- 50 def childImage(self, ci): 51 self.image.child.image_file = ci 52 53class MemBus(CoherentBus): 54 badaddr_responder = BadAddr() 55 default = Self.badaddr_responder.pio 56 57 | 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 41 unchanged lines hidden (view full) --- 50 def childImage(self, ci): 51 self.image.child.image_file = ci 52 53class MemBus(CoherentBus): 54 badaddr_responder = BadAddr() 55 default = Self.badaddr_responder.pio 56 57 |
58def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None): | 58def makeLinuxAlphaSystem(mem_mode, mdesc = None): |
59 IO_address_space_base = 0x80000000000 60 class BaseTsunami(Tsunami): 61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 62 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 63 pci_func=0, pci_dev=0, pci_bus=0) 64 65 self = LinuxAlphaSystem() 66 if not mdesc: 67 # generic system 68 mdesc = SysConfig() 69 self.readfile = mdesc.script() 70 self.iobus = NoncoherentBus() 71 self.membus = MemBus() 72 # By default the bridge responds to all addresses above the I/O 73 # base address (including the PCI config space) 74 self.bridge = Bridge(delay='50ns', 75 ranges = [AddrRange(IO_address_space_base, Addr.max)]) | 59 IO_address_space_base = 0x80000000000 60 class BaseTsunami(Tsunami): 61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 62 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 63 pci_func=0, pci_dev=0, pci_bus=0) 64 65 self = LinuxAlphaSystem() 66 if not mdesc: 67 # generic system 68 mdesc = SysConfig() 69 self.readfile = mdesc.script() 70 self.iobus = NoncoherentBus() 71 self.membus = MemBus() 72 # By default the bridge responds to all addresses above the I/O 73 # base address (including the PCI config space) 74 self.bridge = Bridge(delay='50ns', 75 ranges = [AddrRange(IO_address_space_base, Addr.max)]) |
76 self.physmem = MemClass(range = AddrRange(mdesc.mem())) 77 self.mem_ranges = [self.physmem.range] | 76 self.mem_ranges = [AddrRange(mdesc.mem())] |
78 self.bridge.master = self.iobus.slave 79 self.bridge.slave = self.membus.master | 77 self.bridge.master = self.iobus.slave 78 self.bridge.slave = self.membus.master |
80 self.physmem.port = self.membus.master | |
81 self.disk0 = CowIdeDisk(driveID='master') 82 self.disk2 = CowIdeDisk(driveID='master') 83 self.disk0.childImage(mdesc.disk()) 84 self.disk2.childImage(disk('linux-bigswap2.img')) 85 self.tsunami = BaseTsunami() 86 self.tsunami.attachIO(self.iobus) 87 self.tsunami.ide.pio = self.iobus.master 88 self.tsunami.ide.config = self.iobus.master --- 10 unchanged lines hidden (view full) --- 99 self.pal = binary('ts_osfpal') 100 self.console = binary('console') 101 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 102 103 self.system_port = self.membus.slave 104 105 return self 106 | 79 self.disk0 = CowIdeDisk(driveID='master') 80 self.disk2 = CowIdeDisk(driveID='master') 81 self.disk0.childImage(mdesc.disk()) 82 self.disk2.childImage(disk('linux-bigswap2.img')) 83 self.tsunami = BaseTsunami() 84 self.tsunami.attachIO(self.iobus) 85 self.tsunami.ide.pio = self.iobus.master 86 self.tsunami.ide.config = self.iobus.master --- 10 unchanged lines hidden (view full) --- 97 self.pal = binary('ts_osfpal') 98 self.console = binary('console') 99 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 100 101 self.system_port = self.membus.slave 102 103 return self 104 |
107def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None): | 105def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): |
108 class BaseTsunami(Tsunami): 109 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 110 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 111 pci_func=0, pci_dev=0, pci_bus=0) | 106 class BaseTsunami(Tsunami): 107 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 108 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 109 pci_func=0, pci_dev=0, pci_bus=0) |
112 113 physmem = MemClass(range = AddrRange(mdesc.mem())) 114 self = LinuxAlphaSystem(physmem = physmem) 115 self.mem_ranges = [self.physmem.range] | 110 self = LinuxAlphaSystem() 111 self.mem_ranges = [AddrRange(mdesc.mem())] |
116 if not mdesc: 117 # generic system 118 mdesc = SysConfig() 119 self.readfile = mdesc.script() 120 121 # Create pio bus to connect all device pio ports to rubymem's pio port 122 self.piobus = NoncoherentBus() 123 | 112 if not mdesc: 113 # generic system 114 mdesc = SysConfig() 115 self.readfile = mdesc.script() 116 117 # Create pio bus to connect all device pio ports to rubymem's pio port 118 self.piobus = NoncoherentBus() 119 |
124 # 125 # Pio functional accesses from devices need direct access to memory 126 # RubyPort currently does support functional accesses. Therefore provide 127 # the piobus a direct connection to physical memory 128 # 129 self.piobus.master = physmem.port 130 | |
131 self.disk0 = CowIdeDisk(driveID='master') 132 self.disk2 = CowIdeDisk(driveID='master') 133 self.disk0.childImage(mdesc.disk()) 134 self.disk2.childImage(disk('linux-bigswap2.img')) 135 self.tsunami = BaseTsunami() 136 self.tsunami.attachIO(self.piobus) 137 self.tsunami.ide.pio = self.piobus.master 138 self.tsunami.ide.config = self.piobus.master --- 13 unchanged lines hidden (view full) --- 152 self.terminal = Terminal() 153 self.kernel = binary('vmlinux') 154 self.pal = binary('ts_osfpal') 155 self.console = binary('console') 156 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 157 158 return self 159 | 120 self.disk0 = CowIdeDisk(driveID='master') 121 self.disk2 = CowIdeDisk(driveID='master') 122 self.disk0.childImage(mdesc.disk()) 123 self.disk2.childImage(disk('linux-bigswap2.img')) 124 self.tsunami = BaseTsunami() 125 self.tsunami.attachIO(self.piobus) 126 self.tsunami.ide.pio = self.piobus.master 127 self.tsunami.ide.config = self.piobus.master --- 13 unchanged lines hidden (view full) --- 141 self.terminal = Terminal() 142 self.kernel = binary('vmlinux') 143 self.pal = binary('ts_osfpal') 144 self.console = binary('console') 145 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 146 147 return self 148 |
160def makeSparcSystem(mem_mode, MemClass, mdesc = None): | 149def makeSparcSystem(mem_mode, mdesc = None): |
161 # Constants from iob.cc and uart8250.cc 162 iob_man_addr = 0x9800000000 163 uart_pio_size = 8 164 165 class CowMmDisk(MmDisk): 166 image = CowDiskImage(child=RawDiskImage(read_only=True), 167 read_only=False) 168 --- 6 unchanged lines hidden (view full) --- 175 mdesc = SysConfig() 176 self.readfile = mdesc.script() 177 self.iobus = NoncoherentBus() 178 self.membus = MemBus() 179 self.bridge = Bridge(delay='50ns') 180 self.t1000 = T1000() 181 self.t1000.attachOnChipIO(self.membus) 182 self.t1000.attachIO(self.iobus) | 150 # Constants from iob.cc and uart8250.cc 151 iob_man_addr = 0x9800000000 152 uart_pio_size = 8 153 154 class CowMmDisk(MmDisk): 155 image = CowDiskImage(child=RawDiskImage(read_only=True), 156 read_only=False) 157 --- 6 unchanged lines hidden (view full) --- 164 mdesc = SysConfig() 165 self.readfile = mdesc.script() 166 self.iobus = NoncoherentBus() 167 self.membus = MemBus() 168 self.bridge = Bridge(delay='50ns') 169 self.t1000 = T1000() 170 self.t1000.attachOnChipIO(self.membus) 171 self.t1000.attachIO(self.iobus) |
183 self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB')) 184 self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB')) 185 self.mem_ranges = [self.physmem.range, self.physmem2.range] | 172 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 173 AddrRange(Addr('2GB'), size ='256MB')] |
186 self.bridge.master = self.iobus.slave 187 self.bridge.slave = self.membus.master | 174 self.bridge.master = self.iobus.slave 175 self.bridge.slave = self.membus.master |
188 self.physmem.port = self.membus.master 189 self.physmem2.port = self.membus.master | |
190 self.rom.port = self.membus.master 191 self.nvram.port = self.membus.master 192 self.hypervisor_desc.port = self.membus.master 193 self.partition_desc.port = self.membus.master 194 self.intrctrl = IntrControl() 195 self.disk0 = CowMmDisk() 196 self.disk0.childImage(disk('disk.s10hw2')) 197 self.disk0.pio = self.iobus.master --- 22 unchanged lines hidden (view full) --- 220 self.nvram_bin = binary('nvram1') 221 self.hypervisor_desc_bin = binary('1up-hv.bin') 222 self.partition_desc_bin = binary('1up-md.bin') 223 224 self.system_port = self.membus.slave 225 226 return self 227 | 176 self.rom.port = self.membus.master 177 self.nvram.port = self.membus.master 178 self.hypervisor_desc.port = self.membus.master 179 self.partition_desc.port = self.membus.master 180 self.intrctrl = IntrControl() 181 self.disk0 = CowMmDisk() 182 self.disk0.childImage(disk('disk.s10hw2')) 183 self.disk0.pio = self.iobus.master --- 22 unchanged lines hidden (view full) --- 206 self.nvram_bin = binary('nvram1') 207 self.hypervisor_desc_bin = binary('1up-hv.bin') 208 self.partition_desc_bin = binary('1up-md.bin') 209 210 self.system_port = self.membus.slave 211 212 return self 213 |
228def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None, | 214def makeArmSystem(mem_mode, machine_type, mdesc = None, |
229 dtb_filename = None, bare_metal=False): 230 assert machine_type 231 232 if bare_metal: 233 self = ArmSystem() 234 else: 235 self = LinuxArmSystem() 236 --- 31 unchanged lines hidden (view full) --- 268 try: 269 self.realview.ide.disks = [self.cf0] 270 except: 271 self.realview.cf_ctrl.disks = [self.cf0] 272 273 if bare_metal: 274 # EOT character on UART will end the simulation 275 self.realview.uart.end_on_eot = True | 215 dtb_filename = None, bare_metal=False): 216 assert machine_type 217 218 if bare_metal: 219 self = ArmSystem() 220 else: 221 self = LinuxArmSystem() 222 --- 31 unchanged lines hidden (view full) --- 254 try: 255 self.realview.ide.disks = [self.cf0] 256 except: 257 self.realview.cf_ctrl.disks = [self.cf0] 258 259 if bare_metal: 260 # EOT character on UART will end the simulation 261 self.realview.uart.end_on_eot = True |
276 self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem()))) 277 self.mem_ranges = [self.physmem.range] | 262 self.mem_ranges = [AddrRange(mdesc.mem())] |
278 else: 279 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 280 if dtb_filename is not None: 281 self.dtb_filename = dtb_filename 282 self.machine_type = machine_type 283 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 284 print "The currently selected ARM platforms doesn't support" 285 print " the amount of DRAM you've selected. Please try" 286 print " another platform" 287 sys.exit(1) 288 289 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 290 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() | 263 else: 264 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 265 if dtb_filename is not None: 266 self.dtb_filename = dtb_filename 267 self.machine_type = machine_type 268 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 269 print "The currently selected ARM platforms doesn't support" 270 print " the amount of DRAM you've selected. Please try" 271 print " another platform" 272 sys.exit(1) 273 274 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 275 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() |
291 292 self.physmem = MemClass(range = AddrRange(self.realview.mem_start_addr, 293 size = mdesc.mem()), 294 conf_table_reported = True) 295 self.mem_ranges = [self.physmem.range] | 276 self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 277 size = mdesc.mem())] |
296 self.realview.setupBootLoader(self.membus, self, binary) 297 self.gic_cpu_addr = self.realview.gic.cpu_addr 298 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 299 300 if mdesc.disk().lower().count('android'): 301 boot_flags += " init=/init " 302 self.boot_osflags = boot_flags | 278 self.realview.setupBootLoader(self.membus, self, binary) 279 self.gic_cpu_addr = self.realview.gic.cpu_addr 280 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 281 282 if mdesc.disk().lower().count('android'): 283 boot_flags += " init=/init " 284 self.boot_osflags = boot_flags |
303 304 self.physmem.port = self.membus.master | |
305 self.realview.attachOnChipIO(self.membus, self.bridge) 306 self.realview.attachIO(self.iobus) 307 self.intrctrl = IntrControl() 308 self.terminal = Terminal() 309 self.vncserver = VncServer() 310 311 self.system_port = self.membus.slave 312 313 return self 314 315 | 285 self.realview.attachOnChipIO(self.membus, self.bridge) 286 self.realview.attachIO(self.iobus) 287 self.intrctrl = IntrControl() 288 self.terminal = Terminal() 289 self.vncserver = VncServer() 290 291 self.system_port = self.membus.slave 292 293 return self 294 295 |
316def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None): | 296def makeLinuxMipsSystem(mem_mode, mdesc = None): |
317 class BaseMalta(Malta): 318 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 319 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 320 pci_func=0, pci_dev=0, pci_bus=0) 321 322 self = LinuxMipsSystem() 323 if not mdesc: 324 # generic system 325 mdesc = SysConfig() 326 self.readfile = mdesc.script() 327 self.iobus = NoncoherentBus() 328 self.membus = MemBus() 329 self.bridge = Bridge(delay='50ns') | 297 class BaseMalta(Malta): 298 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 299 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 300 pci_func=0, pci_dev=0, pci_bus=0) 301 302 self = LinuxMipsSystem() 303 if not mdesc: 304 # generic system 305 mdesc = SysConfig() 306 self.readfile = mdesc.script() 307 self.iobus = NoncoherentBus() 308 self.membus = MemBus() 309 self.bridge = Bridge(delay='50ns') |
330 self.physmem = MemClass(range = AddrRange('1GB')) 331 self.mem_ranges = [self.physmem.range] | 310 self.mem_ranges = [AddrRange('1GB')] |
332 self.bridge.master = self.iobus.slave 333 self.bridge.slave = self.membus.master | 311 self.bridge.master = self.iobus.slave 312 self.bridge.slave = self.membus.master |
334 self.physmem.port = self.membus.master | |
335 self.disk0 = CowIdeDisk(driveID='master') 336 self.disk2 = CowIdeDisk(driveID='master') 337 self.disk0.childImage(mdesc.disk()) 338 self.disk2.childImage(disk('linux-bigswap2.img')) 339 self.malta = BaseMalta() 340 self.malta.attachIO(self.iobus) 341 self.malta.ide.pio = self.iobus.master 342 self.malta.ide.config = self.iobus.master --- 21 unchanged lines hidden (view full) --- 364def connectX86ClassicSystem(x86_sys, numCPUs): 365 # Constants similar to x86_traits.hh 366 IO_address_space_base = 0x8000000000000000 367 pci_config_address_space_base = 0xc000000000000000 368 interrupts_address_space_base = 0xa000000000000000 369 APIC_range_size = 1 << 12; 370 371 x86_sys.membus = MemBus() | 313 self.disk0 = CowIdeDisk(driveID='master') 314 self.disk2 = CowIdeDisk(driveID='master') 315 self.disk0.childImage(mdesc.disk()) 316 self.disk2.childImage(disk('linux-bigswap2.img')) 317 self.malta = BaseMalta() 318 self.malta.attachIO(self.iobus) 319 self.malta.ide.pio = self.iobus.master 320 self.malta.ide.config = self.iobus.master --- 21 unchanged lines hidden (view full) --- 342def connectX86ClassicSystem(x86_sys, numCPUs): 343 # Constants similar to x86_traits.hh 344 IO_address_space_base = 0x8000000000000000 345 pci_config_address_space_base = 0xc000000000000000 346 interrupts_address_space_base = 0xa000000000000000 347 APIC_range_size = 1 << 12; 348 349 x86_sys.membus = MemBus() |
372 x86_sys.physmem.port = x86_sys.membus.master | |
373 374 # North Bridge 375 x86_sys.iobus = NoncoherentBus() 376 x86_sys.bridge = Bridge(delay='50ns') 377 x86_sys.bridge.master = x86_sys.iobus.slave 378 x86_sys.bridge.slave = x86_sys.membus.master 379 # Allow the bridge to pass through the IO APIC (two pages), 380 # everything in the IO address range up to the local APIC, and --- 23 unchanged lines hidden (view full) --- 404 x86_sys.pc.attachIO(x86_sys.iobus) 405 406 x86_sys.system_port = x86_sys.membus.slave 407 408def connectX86RubySystem(x86_sys): 409 # North Bridge 410 x86_sys.piobus = NoncoherentBus() 411 | 350 351 # North Bridge 352 x86_sys.iobus = NoncoherentBus() 353 x86_sys.bridge = Bridge(delay='50ns') 354 x86_sys.bridge.master = x86_sys.iobus.slave 355 x86_sys.bridge.slave = x86_sys.membus.master 356 # Allow the bridge to pass through the IO APIC (two pages), 357 # everything in the IO address range up to the local APIC, and --- 23 unchanged lines hidden (view full) --- 381 x86_sys.pc.attachIO(x86_sys.iobus) 382 383 x86_sys.system_port = x86_sys.membus.slave 384 385def connectX86RubySystem(x86_sys): 386 # North Bridge 387 x86_sys.piobus = NoncoherentBus() 388 |
412 # 413 # Pio functional accesses from devices need direct access to memory 414 # RubyPort currently does support functional accesses. Therefore provide 415 # the piobus a direct connection to physical memory 416 # 417 x86_sys.piobus.master = x86_sys.physmem.port | |
418 # add the ide to the list of dma devices that later need to attach to 419 # dma controllers 420 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 421 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 422 423 | 389 # add the ide to the list of dma devices that later need to attach to 390 # dma controllers 391 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 392 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 393 394 |
424def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None, | 395def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, |
425 Ruby = False): 426 if self == None: 427 self = X86System() 428 429 if not mdesc: 430 # generic system 431 mdesc = SysConfig() 432 self.readfile = mdesc.script() 433 434 self.mem_mode = mem_mode 435 436 # Physical memory | 396 Ruby = False): 397 if self == None: 398 self = X86System() 399 400 if not mdesc: 401 # generic system 402 mdesc = SysConfig() 403 self.readfile = mdesc.script() 404 405 self.mem_mode = mem_mode 406 407 # Physical memory |
437 self.physmem = MemClass(range = AddrRange(mdesc.mem())) 438 self.mem_ranges = [self.physmem.range] | 408 self.mem_ranges = [AddrRange(mdesc.mem())] |
439 440 # Platform 441 self.pc = Pc() 442 443 # Create and connect the busses required by each memory system 444 if Ruby: 445 connectX86RubySystem(self) 446 else: --- 66 unchanged lines hidden (view full) --- 513 base_entries.append(assign_to_apic) 514 assignISAInt(0, 2) 515 assignISAInt(1, 1) 516 for i in range(3, 15): 517 assignISAInt(i, i) 518 self.intel_mp_table.base_entries = base_entries 519 self.intel_mp_table.ext_entries = ext_entries 520 | 409 410 # Platform 411 self.pc = Pc() 412 413 # Create and connect the busses required by each memory system 414 if Ruby: 415 connectX86RubySystem(self) 416 else: --- 66 unchanged lines hidden (view full) --- 483 base_entries.append(assign_to_apic) 484 assignISAInt(0, 2) 485 assignISAInt(1, 1) 486 for i in range(3, 15): 487 assignISAInt(i, i) 488 self.intel_mp_table.base_entries = base_entries 489 self.intel_mp_table.ext_entries = ext_entries 490 |
521def makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, | 491def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, |
522 Ruby = False): 523 self = LinuxX86System() 524 525 # Build up the x86 system and then specialize it for Linux | 492 Ruby = False): 493 self = LinuxX86System() 494 495 # Build up the x86 system and then specialize it for Linux |
526 makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby) | 496 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) |
527 528 # We assume below that there's at least 1MB of memory. We'll require 2 529 # just to avoid corner cases. | 497 498 # We assume below that there's at least 1MB of memory. We'll require 2 499 # just to avoid corner cases. |
530 phys_mem_size = sum(map(lambda mem: mem.range.size(), 531 self.memories.unproxy(self))) | 500 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) |
532 assert(phys_mem_size >= 0x200000) 533 534 self.e820_table.entries = \ 535 [ 536 # Mark the first megabyte of memory as reserved 537 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 538 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 539 # Mark the rest as available --- 33 unchanged lines hidden --- | 501 assert(phys_mem_size >= 0x200000) 502 503 self.e820_table.entries = \ 504 [ 505 # Mark the first megabyte of memory as reserved 506 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 507 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 508 # Mark the rest as available --- 33 unchanged lines hidden --- |