FSConfig.py (8931:7a1dfb191e3f) | FSConfig.py (9036:6385cf85bf12) |
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1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 36 unchanged lines hidden (view full) --- 45 46class CowIdeDisk(IdeDisk): 47 image = CowDiskImage(child=RawDiskImage(read_only=True), 48 read_only=False) 49 50 def childImage(self, ci): 51 self.image.child.image_file = ci 52 | 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 36 unchanged lines hidden (view full) --- 45 46class CowIdeDisk(IdeDisk): 47 image = CowDiskImage(child=RawDiskImage(read_only=True), 48 read_only=False) 49 50 def childImage(self, ci): 51 self.image.child.image_file = ci 52 |
53class MemBus(Bus): | 53class MemBus(CoherentBus): |
54 badaddr_responder = BadAddr() 55 default = Self.badaddr_responder.pio 56 57 58def makeLinuxAlphaSystem(mem_mode, mdesc = None): 59 IO_address_space_base = 0x80000000000 60 class BaseTsunami(Tsunami): 61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 62 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 63 pci_func=0, pci_dev=0, pci_bus=0) 64 65 self = LinuxAlphaSystem() 66 if not mdesc: 67 # generic system 68 mdesc = SysConfig() 69 self.readfile = mdesc.script() | 54 badaddr_responder = BadAddr() 55 default = Self.badaddr_responder.pio 56 57 58def makeLinuxAlphaSystem(mem_mode, mdesc = None): 59 IO_address_space_base = 0x80000000000 60 class BaseTsunami(Tsunami): 61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 62 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 63 pci_func=0, pci_dev=0, pci_bus=0) 64 65 self = LinuxAlphaSystem() 66 if not mdesc: 67 # generic system 68 mdesc = SysConfig() 69 self.readfile = mdesc.script() |
70 self.iobus = Bus(bus_id=0) 71 self.membus = MemBus(bus_id=1) | 70 self.iobus = NoncoherentBus() 71 self.membus = MemBus() |
72 # By default the bridge responds to all addresses above the I/O 73 # base address (including the PCI config space) 74 self.bridge = Bridge(delay='50ns', nack_delay='4ns', 75 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 76 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem())) 77 self.bridge.master = self.iobus.slave 78 self.bridge.slave = self.membus.master 79 self.physmem.port = self.membus.master --- 32 unchanged lines hidden (view full) --- 112 physmem = SimpleMemory(range = AddrRange(mdesc.mem())) 113 self = LinuxAlphaSystem(physmem = physmem) 114 if not mdesc: 115 # generic system 116 mdesc = SysConfig() 117 self.readfile = mdesc.script() 118 119 # Create pio bus to connect all device pio ports to rubymem's pio port | 72 # By default the bridge responds to all addresses above the I/O 73 # base address (including the PCI config space) 74 self.bridge = Bridge(delay='50ns', nack_delay='4ns', 75 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 76 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem())) 77 self.bridge.master = self.iobus.slave 78 self.bridge.slave = self.membus.master 79 self.physmem.port = self.membus.master --- 32 unchanged lines hidden (view full) --- 112 physmem = SimpleMemory(range = AddrRange(mdesc.mem())) 113 self = LinuxAlphaSystem(physmem = physmem) 114 if not mdesc: 115 # generic system 116 mdesc = SysConfig() 117 self.readfile = mdesc.script() 118 119 # Create pio bus to connect all device pio ports to rubymem's pio port |
120 self.piobus = Bus(bus_id=0) | 120 self.piobus = NoncoherentBus() |
121 122 # 123 # Pio functional accesses from devices need direct access to memory 124 # RubyPort currently does support functional accesses. Therefore provide 125 # the piobus a direct connection to physical memory 126 # 127 self.piobus.master = physmem.port 128 --- 38 unchanged lines hidden (view full) --- 167 def childImage(self, ci): 168 self.image.child.image_file = ci 169 170 self = SparcSystem() 171 if not mdesc: 172 # generic system 173 mdesc = SysConfig() 174 self.readfile = mdesc.script() | 121 122 # 123 # Pio functional accesses from devices need direct access to memory 124 # RubyPort currently does support functional accesses. Therefore provide 125 # the piobus a direct connection to physical memory 126 # 127 self.piobus.master = physmem.port 128 --- 38 unchanged lines hidden (view full) --- 167 def childImage(self, ci): 168 self.image.child.image_file = ci 169 170 self = SparcSystem() 171 if not mdesc: 172 # generic system 173 mdesc = SysConfig() 174 self.readfile = mdesc.script() |
175 self.iobus = Bus(bus_id=0) 176 self.membus = MemBus(bus_id=1) | 175 self.iobus = NoncoherentBus() 176 self.membus = MemBus() |
177 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 178 self.t1000 = T1000() 179 self.t1000.attachOnChipIO(self.membus) 180 self.t1000.attachIO(self.iobus) 181 self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'), 182 zero = True) 183 self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'), 184 zero = True) --- 47 unchanged lines hidden (view full) --- 232 else: 233 self = LinuxArmSystem() 234 235 if not mdesc: 236 # generic system 237 mdesc = SysConfig() 238 239 self.readfile = mdesc.script() | 177 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 178 self.t1000 = T1000() 179 self.t1000.attachOnChipIO(self.membus) 180 self.t1000.attachIO(self.iobus) 181 self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'), 182 zero = True) 183 self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'), 184 zero = True) --- 47 unchanged lines hidden (view full) --- 232 else: 233 self = LinuxArmSystem() 234 235 if not mdesc: 236 # generic system 237 mdesc = SysConfig() 238 239 self.readfile = mdesc.script() |
240 self.iobus = Bus(bus_id=0) 241 self.membus = MemBus(bus_id=1) | 240 self.iobus = NoncoherentBus() 241 self.membus = MemBus() |
242 self.membus.badaddr_responder.warn_access = "warn" 243 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 244 self.bridge.master = self.iobus.slave 245 self.bridge.slave = self.membus.master 246 247 self.mem_mode = mem_mode 248 249 if machine_type == "RealView_PBX": --- 65 unchanged lines hidden (view full) --- 315 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 316 pci_func=0, pci_dev=0, pci_bus=0) 317 318 self = LinuxMipsSystem() 319 if not mdesc: 320 # generic system 321 mdesc = SysConfig() 322 self.readfile = mdesc.script() | 242 self.membus.badaddr_responder.warn_access = "warn" 243 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 244 self.bridge.master = self.iobus.slave 245 self.bridge.slave = self.membus.master 246 247 self.mem_mode = mem_mode 248 249 if machine_type == "RealView_PBX": --- 65 unchanged lines hidden (view full) --- 315 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 316 pci_func=0, pci_dev=0, pci_bus=0) 317 318 self = LinuxMipsSystem() 319 if not mdesc: 320 # generic system 321 mdesc = SysConfig() 322 self.readfile = mdesc.script() |
323 self.iobus = Bus(bus_id=0) 324 self.membus = MemBus(bus_id=1) | 323 self.iobus = NoncoherentBus() 324 self.membus = MemBus() |
325 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 326 self.physmem = SimpleMemory(range = AddrRange('1GB')) 327 self.bridge.master = self.iobus.slave 328 self.bridge.slave = self.membus.master 329 self.physmem.port = self.membus.master 330 self.disk0 = CowIdeDisk(driveID='master') 331 self.disk2 = CowIdeDisk(driveID='master') 332 self.disk0.childImage(mdesc.disk()) --- 25 unchanged lines hidden (view full) --- 358 359def connectX86ClassicSystem(x86_sys, numCPUs): 360 # Constants similar to x86_traits.hh 361 IO_address_space_base = 0x8000000000000000 362 pci_config_address_space_base = 0xc000000000000000 363 interrupts_address_space_base = 0xa000000000000000 364 APIC_range_size = 1 << 12; 365 | 325 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 326 self.physmem = SimpleMemory(range = AddrRange('1GB')) 327 self.bridge.master = self.iobus.slave 328 self.bridge.slave = self.membus.master 329 self.physmem.port = self.membus.master 330 self.disk0 = CowIdeDisk(driveID='master') 331 self.disk2 = CowIdeDisk(driveID='master') 332 self.disk0.childImage(mdesc.disk()) --- 25 unchanged lines hidden (view full) --- 358 359def connectX86ClassicSystem(x86_sys, numCPUs): 360 # Constants similar to x86_traits.hh 361 IO_address_space_base = 0x8000000000000000 362 pci_config_address_space_base = 0xc000000000000000 363 interrupts_address_space_base = 0xa000000000000000 364 APIC_range_size = 1 << 12; 365 |
366 x86_sys.membus = MemBus(bus_id=1) | 366 x86_sys.membus = MemBus() |
367 x86_sys.physmem.port = x86_sys.membus.master 368 369 # North Bridge | 367 x86_sys.physmem.port = x86_sys.membus.master 368 369 # North Bridge |
370 x86_sys.iobus = Bus(bus_id=0) | 370 x86_sys.iobus = NoncoherentBus() |
371 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 372 x86_sys.bridge.master = x86_sys.iobus.slave 373 x86_sys.bridge.slave = x86_sys.membus.master 374 # Allow the bridge to pass through the IO APIC (two pages), 375 # everything in the IO address range up to the local APIC, and 376 # then the entire PCI address space and beyond 377 x86_sys.bridge.ranges = \ 378 [ --- 18 unchanged lines hidden (view full) --- 397 398 # connect the io bus 399 x86_sys.pc.attachIO(x86_sys.iobus) 400 401 x86_sys.system_port = x86_sys.membus.slave 402 403def connectX86RubySystem(x86_sys): 404 # North Bridge | 371 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 372 x86_sys.bridge.master = x86_sys.iobus.slave 373 x86_sys.bridge.slave = x86_sys.membus.master 374 # Allow the bridge to pass through the IO APIC (two pages), 375 # everything in the IO address range up to the local APIC, and 376 # then the entire PCI address space and beyond 377 x86_sys.bridge.ranges = \ 378 [ --- 18 unchanged lines hidden (view full) --- 397 398 # connect the io bus 399 x86_sys.pc.attachIO(x86_sys.iobus) 400 401 x86_sys.system_port = x86_sys.membus.slave 402 403def connectX86RubySystem(x86_sys): 404 # North Bridge |
405 x86_sys.piobus = Bus(bus_id=0) | 405 x86_sys.piobus = NoncoherentBus() |
406 407 # 408 # Pio functional accesses from devices need direct access to memory 409 # RubyPort currently does support functional accesses. Therefore provide 410 # the piobus a direct connection to physical memory 411 # 412 x86_sys.piobus.master = x86_sys.physmem.port 413 # add the ide to the list of dma devices that later need to attach to --- 218 unchanged lines hidden --- | 406 407 # 408 # Pio functional accesses from devices need direct access to memory 409 # RubyPort currently does support functional accesses. Therefore provide 410 # the piobus a direct connection to physical memory 411 # 412 x86_sys.piobus.master = x86_sys.physmem.port 413 # add the ide to the list of dma devices that later need to attach to --- 218 unchanged lines hidden --- |