FSConfig.py (4965:ad0e792a5c78) | FSConfig.py (4972:ee5b7df7f436) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 79 unchanged lines hidden (view full) --- 88 89 self = SparcSystem() 90 if not mdesc: 91 # generic system 92 mdesc = SysConfig() 93 self.readfile = mdesc.script() 94 self.iobus = Bus(bus_id=0) 95 self.membus = Bus(bus_id=1) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 79 unchanged lines hidden (view full) --- 88 89 self = SparcSystem() 90 if not mdesc: 91 # generic system 92 mdesc = SysConfig() 93 self.readfile = mdesc.script() 94 self.iobus = Bus(bus_id=0) 95 self.membus = Bus(bus_id=1) |
96 self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') | 96 self.bridge = Bridge(delay='50ns', nack_delay='4ns') |
97 self.t1000 = T1000() 98 self.t1000.attachOnChipIO(self.membus) 99 self.t1000.attachIO(self.iobus) 100 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 101 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 102 self.bridge.side_a = self.iobus.port 103 self.bridge.side_b = self.membus.port 104 self.physmem.port = self.membus.port --- 30 unchanged lines hidden --- | 97 self.t1000 = T1000() 98 self.t1000.attachOnChipIO(self.membus) 99 self.t1000.attachIO(self.iobus) 100 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 101 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 102 self.bridge.side_a = self.iobus.port 103 self.bridge.side_b = self.membus.port 104 self.physmem.port = self.membus.port --- 30 unchanged lines hidden --- |