FSConfig.py (10697:71c40e5c8bd4) | FSConfig.py (10720:67b3e74de9ae) |
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1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 36 unchanged lines hidden (view full) --- 45 46class CowIdeDisk(IdeDisk): 47 image = CowDiskImage(child=RawDiskImage(read_only=True), 48 read_only=False) 49 50 def childImage(self, ci): 51 self.image.child.image_file = ci 52 | 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 36 unchanged lines hidden (view full) --- 45 46class CowIdeDisk(IdeDisk): 47 image = CowDiskImage(child=RawDiskImage(read_only=True), 48 read_only=False) 49 50 def childImage(self, ci): 51 self.image.child.image_file = ci 52 |
53class MemBus(CoherentXBar): | 53class MemBus(SystemXBar): |
54 badaddr_responder = BadAddr() 55 default = Self.badaddr_responder.pio 56 57 58def fillInCmdline(mdesc, template, **kwargs): 59 kwargs.setdefault('disk', mdesc.disk()) 60 kwargs.setdefault('rootdev', mdesc.rootdev()) 61 kwargs.setdefault('mem', mdesc.mem()) --- 11 unchanged lines hidden (view full) --- 73 if not mdesc: 74 # generic system 75 mdesc = SysConfig() 76 self.readfile = mdesc.script() 77 78 self.tsunami = BaseTsunami() 79 80 # Create the io bus to connect all device ports | 54 badaddr_responder = BadAddr() 55 default = Self.badaddr_responder.pio 56 57 58def fillInCmdline(mdesc, template, **kwargs): 59 kwargs.setdefault('disk', mdesc.disk()) 60 kwargs.setdefault('rootdev', mdesc.rootdev()) 61 kwargs.setdefault('mem', mdesc.mem()) --- 11 unchanged lines hidden (view full) --- 73 if not mdesc: 74 # generic system 75 mdesc = SysConfig() 76 self.readfile = mdesc.script() 77 78 self.tsunami = BaseTsunami() 79 80 # Create the io bus to connect all device ports |
81 self.iobus = NoncoherentXBar() | 81 self.iobus = IOXBar() |
82 self.tsunami.attachIO(self.iobus) 83 84 self.tsunami.ide.pio = self.iobus.master 85 self.tsunami.ide.config = self.iobus.master 86 87 self.tsunami.ethernet.pio = self.iobus.master 88 self.tsunami.ethernet.config = self.iobus.master 89 --- 48 unchanged lines hidden (view full) --- 138 def childImage(self, ci): 139 self.image.child.image_file = ci 140 141 self = SparcSystem() 142 if not mdesc: 143 # generic system 144 mdesc = SysConfig() 145 self.readfile = mdesc.script() | 82 self.tsunami.attachIO(self.iobus) 83 84 self.tsunami.ide.pio = self.iobus.master 85 self.tsunami.ide.config = self.iobus.master 86 87 self.tsunami.ethernet.pio = self.iobus.master 88 self.tsunami.ethernet.config = self.iobus.master 89 --- 48 unchanged lines hidden (view full) --- 138 def childImage(self, ci): 139 self.image.child.image_file = ci 140 141 self = SparcSystem() 142 if not mdesc: 143 # generic system 144 mdesc = SysConfig() 145 self.readfile = mdesc.script() |
146 self.iobus = NoncoherentXBar() | 146 self.iobus = IOXBar() |
147 self.membus = MemBus() 148 self.bridge = Bridge(delay='50ns') 149 self.t1000 = T1000() 150 self.t1000.attachOnChipIO(self.membus) 151 self.t1000.attachIO(self.iobus) 152 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 153 AddrRange(Addr('2GB'), size ='256MB')] 154 self.bridge.master = self.iobus.slave --- 45 unchanged lines hidden (view full) --- 200 else: 201 self = LinuxArmSystem() 202 203 if not mdesc: 204 # generic system 205 mdesc = SysConfig() 206 207 self.readfile = mdesc.script() | 147 self.membus = MemBus() 148 self.bridge = Bridge(delay='50ns') 149 self.t1000 = T1000() 150 self.t1000.attachOnChipIO(self.membus) 151 self.t1000.attachIO(self.iobus) 152 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 153 AddrRange(Addr('2GB'), size ='256MB')] 154 self.bridge.master = self.iobus.slave --- 45 unchanged lines hidden (view full) --- 200 else: 201 self = LinuxArmSystem() 202 203 if not mdesc: 204 # generic system 205 mdesc = SysConfig() 206 207 self.readfile = mdesc.script() |
208 self.iobus = NoncoherentXBar() | 208 self.iobus = IOXBar() |
209 self.membus = MemBus() 210 self.membus.badaddr_responder.warn_access = "warn" 211 self.bridge = Bridge(delay='50ns') 212 self.bridge.master = self.iobus.slave 213 self.bridge.slave = self.membus.master 214 215 self.mem_mode = mem_mode 216 --- 89 unchanged lines hidden (view full) --- 306 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 307 pci_func=0, pci_dev=0, pci_bus=0) 308 309 self = LinuxMipsSystem() 310 if not mdesc: 311 # generic system 312 mdesc = SysConfig() 313 self.readfile = mdesc.script() | 209 self.membus = MemBus() 210 self.membus.badaddr_responder.warn_access = "warn" 211 self.bridge = Bridge(delay='50ns') 212 self.bridge.master = self.iobus.slave 213 self.bridge.slave = self.membus.master 214 215 self.mem_mode = mem_mode 216 --- 89 unchanged lines hidden (view full) --- 306 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 307 pci_func=0, pci_dev=0, pci_bus=0) 308 309 self = LinuxMipsSystem() 310 if not mdesc: 311 # generic system 312 mdesc = SysConfig() 313 self.readfile = mdesc.script() |
314 self.iobus = NoncoherentXBar() | 314 self.iobus = IOXBar() |
315 self.membus = MemBus() 316 self.bridge = Bridge(delay='50ns') 317 self.mem_ranges = [AddrRange('1GB')] 318 self.bridge.master = self.iobus.slave 319 self.bridge.slave = self.membus.master 320 self.disk0 = CowIdeDisk(driveID='master') 321 self.disk2 = CowIdeDisk(driveID='master') 322 self.disk0.childImage(mdesc.disk()) --- 30 unchanged lines hidden (view full) --- 353 IO_address_space_base = 0x8000000000000000 354 pci_config_address_space_base = 0xc000000000000000 355 interrupts_address_space_base = 0xa000000000000000 356 APIC_range_size = 1 << 12; 357 358 x86_sys.membus = MemBus() 359 360 # North Bridge | 315 self.membus = MemBus() 316 self.bridge = Bridge(delay='50ns') 317 self.mem_ranges = [AddrRange('1GB')] 318 self.bridge.master = self.iobus.slave 319 self.bridge.slave = self.membus.master 320 self.disk0 = CowIdeDisk(driveID='master') 321 self.disk2 = CowIdeDisk(driveID='master') 322 self.disk0.childImage(mdesc.disk()) --- 30 unchanged lines hidden (view full) --- 353 IO_address_space_base = 0x8000000000000000 354 pci_config_address_space_base = 0xc000000000000000 355 interrupts_address_space_base = 0xa000000000000000 356 APIC_range_size = 1 << 12; 357 358 x86_sys.membus = MemBus() 359 360 # North Bridge |
361 x86_sys.iobus = NoncoherentXBar() | 361 x86_sys.iobus = IOXBar() |
362 x86_sys.bridge = Bridge(delay='50ns') 363 x86_sys.bridge.master = x86_sys.iobus.slave 364 x86_sys.bridge.slave = x86_sys.membus.master 365 # Allow the bridge to pass through: 366 # 1) kernel configured PCI device memory map address: address range 367 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 368 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 369 # 3) everything in the IO address range up to the local APIC, and --- 19 unchanged lines hidden (view full) --- 389 390 # connect the io bus 391 x86_sys.pc.attachIO(x86_sys.iobus) 392 393 x86_sys.system_port = x86_sys.membus.slave 394 395def connectX86RubySystem(x86_sys): 396 # North Bridge | 362 x86_sys.bridge = Bridge(delay='50ns') 363 x86_sys.bridge.master = x86_sys.iobus.slave 364 x86_sys.bridge.slave = x86_sys.membus.master 365 # Allow the bridge to pass through: 366 # 1) kernel configured PCI device memory map address: address range 367 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 368 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 369 # 3) everything in the IO address range up to the local APIC, and --- 19 unchanged lines hidden (view full) --- 389 390 # connect the io bus 391 x86_sys.pc.attachIO(x86_sys.iobus) 392 393 x86_sys.system_port = x86_sys.membus.slave 394 395def connectX86RubySystem(x86_sys): 396 # North Bridge |
397 x86_sys.iobus = NoncoherentXBar() | 397 x86_sys.iobus = IOXBar() |
398 399 # add the ide to the list of dma devices that later need to attach to 400 # dma controllers 401 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 402 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 403 404 405def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): --- 183 unchanged lines hidden --- | 398 399 # add the ide to the list of dma devices that later need to attach to 400 # dma controllers 401 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 402 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 403 404 405def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): --- 183 unchanged lines hidden --- |