1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44
45class CowIdeDisk(IdeDisk):
46 image = CowDiskImage(child=RawDiskImage(read_only=True),
47 read_only=False)
48
49 def childImage(self, ci):
50 self.image.child.image_file = ci
51
52class MemBus(Bus):
53 badaddr_responder = BadAddr()
54 default = Self.badaddr_responder.pio
55
56
57def makeLinuxAlphaSystem(mem_mode, mdesc = None):
58 class BaseTsunami(Tsunami):
59 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
60 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
61 pci_func=0, pci_dev=0, pci_bus=0)
62
63 self = LinuxAlphaSystem()
64 if not mdesc:
65 # generic system
66 mdesc = SysConfig()
67 self.readfile = mdesc.script()
68 self.iobus = Bus(bus_id=0)
69 self.membus = MemBus(bus_id=1)
70 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
71 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
72 self.bridge.side_a = self.iobus.port
73 self.bridge.side_b = self.membus.port
74 self.physmem.port = self.membus.port
75 self.disk0 = CowIdeDisk(driveID='master')
76 self.disk2 = CowIdeDisk(driveID='master')
77 self.disk0.childImage(mdesc.disk())
78 self.disk2.childImage(disk('linux-bigswap2.img'))
79 self.tsunami = BaseTsunami()
80 self.tsunami.attachIO(self.iobus)
81 self.tsunami.ide.pio = self.iobus.port
82 self.tsunami.ethernet.pio = self.iobus.port
83 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
84 read_only = True))
85 self.intrctrl = IntrControl()
86 self.mem_mode = mem_mode
87 self.terminal = Terminal()
88 self.kernel = binary('vmlinux')
89 self.pal = binary('ts_osfpal')
90 self.console = binary('console')
91 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
92
93 return self
94
95def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
96 class BaseTsunami(Tsunami):
97 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
98 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
99 pci_func=0, pci_dev=0, pci_bus=0)
100
101 physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
102 self = LinuxAlphaSystem(physmem = physmem)
103 if not mdesc:
104 # generic system
105 mdesc = SysConfig()
106 self.readfile = mdesc.script()
107
108 # Create pio bus to connect all device pio ports to rubymem's pio port
109 self.piobus = Bus(bus_id=0)
110
111 #
112 # Pio functional accesses from devices need direct access to memory
113 # RubyPort currently does support functional accesses. Therefore provide
114 # the piobus a direct connection to physical memory
115 #
116 self.piobus.port = physmem.port
117
118 self.disk0 = CowIdeDisk(driveID='master')
119 self.disk2 = CowIdeDisk(driveID='master')
120 self.disk0.childImage(mdesc.disk())
121 self.disk2.childImage(disk('linux-bigswap2.img'))
122 self.tsunami = BaseTsunami()
123 self.tsunami.attachIO(self.piobus)
124 self.tsunami.ide.pio = self.piobus.port
125 self.tsunami.ethernet.pio = self.piobus.port
126
127 #
128 # Store the dma devices for later connection to dma ruby ports.
129 # Append an underscore to dma_devices to avoid the SimObjectVector check.
130 #
131 self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
132
133 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
134 read_only = True))
135 self.intrctrl = IntrControl()
136 self.mem_mode = mem_mode
137 self.terminal = Terminal()
138 self.kernel = binary('vmlinux')
139 self.pal = binary('ts_osfpal')
140 self.console = binary('console')
141 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
142
143 return self
144
145def makeSparcSystem(mem_mode, mdesc = None):
146 class CowMmDisk(MmDisk):
147 image = CowDiskImage(child=RawDiskImage(read_only=True),
148 read_only=False)
149
150 def childImage(self, ci):
151 self.image.child.image_file = ci
152
153 self = SparcSystem()
154 if not mdesc:
155 # generic system
156 mdesc = SysConfig()
157 self.readfile = mdesc.script()
158 self.iobus = Bus(bus_id=0)
159 self.membus = MemBus(bus_id=1)
160 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
161 self.t1000 = T1000()
162 self.t1000.attachOnChipIO(self.membus)
163 self.t1000.attachIO(self.iobus)
164 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
165 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
166 self.bridge.side_a = self.iobus.port
167 self.bridge.side_b = self.membus.port
168 self.physmem.port = self.membus.port
169 self.physmem2.port = self.membus.port
170 self.rom.port = self.membus.port
171 self.nvram.port = self.membus.port
172 self.hypervisor_desc.port = self.membus.port
173 self.partition_desc.port = self.membus.port
174 self.intrctrl = IntrControl()
175 self.disk0 = CowMmDisk()
176 self.disk0.childImage(disk('disk.s10hw2'))
177 self.disk0.pio = self.iobus.port
178 self.reset_bin = binary('reset_new.bin')
179 self.hypervisor_bin = binary('q_new.bin')
180 self.openboot_bin = binary('openboot_new.bin')
181 self.nvram_bin = binary('nvram1')
182 self.hypervisor_desc_bin = binary('1up-hv.bin')
183 self.partition_desc_bin = binary('1up-md.bin')
184
185 return self
186
187def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
188 assert machine_type
189
190 if bare_metal:
191 self = ArmSystem()
192 else:
193 self = LinuxArmSystem()
194
195 if not mdesc:
196 # generic system
197 mdesc = SysConfig()
198
199 self.readfile = mdesc.script()
200 self.iobus = Bus(bus_id=0)
201 self.membus = MemBus(bus_id=1)
202 self.membus.badaddr_responder.warn_access = "warn"
203 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
204 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
205 self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
206 file = disk('ael-arm.ext2'))
207 self.bridge.side_a = self.iobus.port
208 self.bridge.side_b = self.membus.port
209 self.physmem.port = self.membus.port
210 self.diskmem.port = self.membus.port
211
212 self.mem_mode = mem_mode
213
214 #self.cf0 = CowIdeDisk(driveID='master')
215 #self.cf0.childImage(mdesc.disk())
216 #self.cf_ctrl = IdeController(disks=[self.cf0],
217 # pci_func = 0, pci_dev = 0, pci_bus = 0,
218 # io_shift = 1, ctrl_offset = 2, Command = 0x1,
219 # BAR0 = 0x18000000, BAR0Size = '16B',
220 # BAR1 = 0x18000100, BAR1Size = '1B',
221 # BAR0LegacyIO = True, BAR1LegacyIO = True,)
222 #self.cf_ctrl.pio = self.iobus.port
223
224 if machine_type == "RealView_PBX":
225 self.realview = RealViewPBX()
226 elif machine_type == "RealView_EB":
227 self.realview = RealViewEB()
228 else:
229 print "Unknown Machine Type"
230 sys.exit(1)
231
232 if bare_metal:
233 # EOT character on UART will end the simulation
234 self.realview.uart.end_on_eot = True
235 else:
236 self.machine_type = machine_type
237 self.kernel = binary('vmlinux.arm')
238 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' + \
239 ' lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000' + \
240 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
241
242 self.realview.attachOnChipIO(self.membus)
243 self.realview.attachIO(self.iobus)
244
245 self.intrctrl = IntrControl()
246 self.terminal = Terminal()
247 self.vncserver = VncServer()
248
249 return self
250
251
252def makeLinuxMipsSystem(mem_mode, mdesc = None):
253 class BaseMalta(Malta):
254 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
255 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
256 pci_func=0, pci_dev=0, pci_bus=0)
257
258 self = LinuxMipsSystem()
259 if not mdesc:
260 # generic system
261 mdesc = SysConfig()
262 self.readfile = mdesc.script()
263 self.iobus = Bus(bus_id=0)
264 self.membus = MemBus(bus_id=1)
265 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
266 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
267 self.bridge.side_a = self.iobus.port
268 self.bridge.side_b = self.membus.port
269 self.physmem.port = self.membus.port
270 self.disk0 = CowIdeDisk(driveID='master')
271 self.disk2 = CowIdeDisk(driveID='master')
272 self.disk0.childImage(mdesc.disk())
273 self.disk2.childImage(disk('linux-bigswap2.img'))
274 self.malta = BaseMalta()
275 self.malta.attachIO(self.iobus)
276 self.malta.ide.pio = self.iobus.port
277 self.malta.ethernet.pio = self.iobus.port
278 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
279 read_only = True))
280 self.intrctrl = IntrControl()
281 self.mem_mode = mem_mode
282 self.terminal = Terminal()
283 self.kernel = binary('mips/vmlinux')
284 self.console = binary('mips/console')
285 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
286
287 return self
288
289def x86IOAddress(port):
290 IO_address_space_base = 0x8000000000000000
291 return IO_address_space_base + port;
292
293def connectX86ClassicSystem(x86_sys):
294 x86_sys.membus = MemBus(bus_id=1)
295 x86_sys.physmem.port = x86_sys.membus.port
296
297 # North Bridge
298 x86_sys.iobus = Bus(bus_id=0)
299 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
300 x86_sys.bridge.side_a = x86_sys.iobus.port
301 x86_sys.bridge.side_b = x86_sys.membus.port
302
303 # connect the io bus
304 x86_sys.pc.attachIO(x86_sys.iobus)
305
306def connectX86RubySystem(x86_sys):
307 # North Bridge
308 x86_sys.piobus = Bus(bus_id=0)
309
310 #
311 # Pio functional accesses from devices need direct access to memory
312 # RubyPort currently does support functional accesses. Therefore provide
313 # the piobus a direct connection to physical memory
314 #
315 x86_sys.piobus.port = x86_sys.physmem.port
316
317 x86_sys.pc.attachIO(x86_sys.piobus)
318
319
320def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
321 if self == None:
322 self = X86System()
323
324 if not mdesc:
325 # generic system
326 mdesc = SysConfig()
327 self.readfile = mdesc.script()
328
329 self.mem_mode = mem_mode
330
331 # Physical memory
332 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
333
334 # Platform
335 self.pc = Pc()
336
337 # Create and connect the busses required by each memory system
338 if Ruby:
339 connectX86RubySystem(self)
340 # add the ide to the list of dma devices that later need to attach to
341 # dma controllers
342 self._dma_devices = [self.pc.south_bridge.ide]
343 else:
344 connectX86ClassicSystem(self)
345
346 self.intrctrl = IntrControl()
347
348 # Disks
349 disk0 = CowIdeDisk(driveID='master')
350 disk2 = CowIdeDisk(driveID='master')
351 disk0.childImage(mdesc.disk())
352 disk2.childImage(disk('linux-bigswap2.img'))
353 self.pc.south_bridge.ide.disks = [disk0, disk2]
354
355 # Add in a Bios information structure.
356 structures = [X86SMBiosBiosInformation()]
357 self.smbios_table.structures = structures
358
359 # Set up the Intel MP table
360 for i in xrange(numCPUs):
361 bp = X86IntelMPProcessor(
362 local_apic_id = i,
363 local_apic_version = 0x14,
364 enable = True,
365 bootstrap = (i == 0))
366 self.intel_mp_table.add_entry(bp)
367 io_apic = X86IntelMPIOAPIC(
368 id = numCPUs,
369 version = 0x11,
370 enable = True,
371 address = 0xfec00000)
372 self.pc.south_bridge.io_apic.apic_id = io_apic.id
373 self.intel_mp_table.add_entry(io_apic)
374 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
375 self.intel_mp_table.add_entry(isa_bus)
376 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
377 self.intel_mp_table.add_entry(pci_bus)
378 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
379 subtractive_decode=True, parent_bus=1)
380 self.intel_mp_table.add_entry(connect_busses)
381 pci_dev4_inta = X86IntelMPIOIntAssignment(
382 interrupt_type = 'INT',
383 polarity = 'ConformPolarity',
384 trigger = 'ConformTrigger',
385 source_bus_id = 1,
386 source_bus_irq = 0 + (4 << 2),
387 dest_io_apic_id = io_apic.id,
388 dest_io_apic_intin = 16)
389 self.intel_mp_table.add_entry(pci_dev4_inta);
390 def assignISAInt(irq, apicPin):
391 assign_8259_to_apic = X86IntelMPIOIntAssignment(
392 interrupt_type = 'ExtInt',
393 polarity = 'ConformPolarity',
394 trigger = 'ConformTrigger',
395 source_bus_id = 0,
396 source_bus_irq = irq,
397 dest_io_apic_id = io_apic.id,
398 dest_io_apic_intin = 0)
399 self.intel_mp_table.add_entry(assign_8259_to_apic)
400 assign_to_apic = X86IntelMPIOIntAssignment(
401 interrupt_type = 'INT',
402 polarity = 'ConformPolarity',
403 trigger = 'ConformTrigger',
404 source_bus_id = 0,
405 source_bus_irq = irq,
406 dest_io_apic_id = io_apic.id,
407 dest_io_apic_intin = apicPin)
408 self.intel_mp_table.add_entry(assign_to_apic)
409 assignISAInt(0, 2)
410 assignISAInt(1, 1)
411 for i in range(3, 15):
412 assignISAInt(i, i)
413
414def setWorkCountOptions(system, options):
415 if options.work_item_id != None:
416 system.work_item_id = options.work_item_id
417 if options.work_begin_cpu_id_exit != None:
418 system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
419 if options.work_end_exit_count != None:
420 system.work_end_exit_count = options.work_end_exit_count
421 if options.work_end_checkpoint_count != None:
422 system.work_end_ckpt_count = options.work_end_checkpoint_count
423 if options.work_begin_exit_count != None:
424 system.work_begin_exit_count = options.work_begin_exit_count
425 if options.work_begin_checkpoint_count != None:
426 system.work_begin_ckpt_count = options.work_begin_checkpoint_count
427 if options.work_cpus_checkpoint_count != None:
428 system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
429
430
431def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
432 self = LinuxX86System()
433
434 # Build up the x86 system and then specialize it for Linux
435 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
436
437 # We assume below that there's at least 1MB of memory. We'll require 2
438 # just to avoid corner cases.
439 assert(self.physmem.range.second.getValue() >= 0x200000)
440
441 # Mark the first megabyte of memory as reserved
442 self.e820_table.entries.append(X86E820Entry(
443 addr = 0,
444 size = '1MB',
445 range_type = 2))
446
447 # Mark the rest as available
448 self.e820_table.entries.append(X86E820Entry(
449 addr = 0x100000,
450 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
451 range_type = 1))
452
453 # Command line
454 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
455 'root=/dev/hda1'
456 return self
457
458
459def makeDualRoot(testSystem, driveSystem, dumpfile):
460 self = Root()
461 self.testsys = testSystem
462 self.drivesys = driveSystem
463 self.etherlink = EtherLink()
464 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
465 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
466
467 if dumpfile:
468 self.etherdump = EtherDump(file=dumpfile)
469 self.etherlink.dump = Parent.etherdump
470
471 return self
472
473def setMipsOptions(TestCPUClass):
474 #CP0 Configuration
475 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
476 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
477 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
478 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
479
480 #CP0 Interrupt Control
481 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
482 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
483
484 # Config Register
485 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
486 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
487 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
488 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
489 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
490 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
491 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
492
493 #Config 1 Register
494 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
495 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
496 # ***VERY IMPORTANT***
497 # Remember to modify CP0_Config1 according to cache specs
498 # Examine file ../common/Cache.py
499 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
500 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
501 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
502 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
503 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
504 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
505 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
506 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
507 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
508 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
509 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
510 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
511 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
512
513 #Config 2 Register
514 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
515 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
516 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
517 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
518 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
519 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
520 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
521 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
522 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
523
524
525 #Config 3 Register
526 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
527 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
528 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
529 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
530 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
531 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
532 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
533 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
534 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
535
536 #SRS Ctl - HSS
537 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
538
539
540 #TestCPUClass.CoreParams.tlb = TLB()
541 #TestCPUClass.CoreParams.UnifiedTLB = 1
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44
45class CowIdeDisk(IdeDisk):
46 image = CowDiskImage(child=RawDiskImage(read_only=True),
47 read_only=False)
48
49 def childImage(self, ci):
50 self.image.child.image_file = ci
51
52class MemBus(Bus):
53 badaddr_responder = BadAddr()
54 default = Self.badaddr_responder.pio
55
56
57def makeLinuxAlphaSystem(mem_mode, mdesc = None):
58 class BaseTsunami(Tsunami):
59 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
60 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
61 pci_func=0, pci_dev=0, pci_bus=0)
62
63 self = LinuxAlphaSystem()
64 if not mdesc:
65 # generic system
66 mdesc = SysConfig()
67 self.readfile = mdesc.script()
68 self.iobus = Bus(bus_id=0)
69 self.membus = MemBus(bus_id=1)
70 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
71 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
72 self.bridge.side_a = self.iobus.port
73 self.bridge.side_b = self.membus.port
74 self.physmem.port = self.membus.port
75 self.disk0 = CowIdeDisk(driveID='master')
76 self.disk2 = CowIdeDisk(driveID='master')
77 self.disk0.childImage(mdesc.disk())
78 self.disk2.childImage(disk('linux-bigswap2.img'))
79 self.tsunami = BaseTsunami()
80 self.tsunami.attachIO(self.iobus)
81 self.tsunami.ide.pio = self.iobus.port
82 self.tsunami.ethernet.pio = self.iobus.port
83 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
84 read_only = True))
85 self.intrctrl = IntrControl()
86 self.mem_mode = mem_mode
87 self.terminal = Terminal()
88 self.kernel = binary('vmlinux')
89 self.pal = binary('ts_osfpal')
90 self.console = binary('console')
91 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
92
93 return self
94
95def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
96 class BaseTsunami(Tsunami):
97 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
98 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
99 pci_func=0, pci_dev=0, pci_bus=0)
100
101 physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
102 self = LinuxAlphaSystem(physmem = physmem)
103 if not mdesc:
104 # generic system
105 mdesc = SysConfig()
106 self.readfile = mdesc.script()
107
108 # Create pio bus to connect all device pio ports to rubymem's pio port
109 self.piobus = Bus(bus_id=0)
110
111 #
112 # Pio functional accesses from devices need direct access to memory
113 # RubyPort currently does support functional accesses. Therefore provide
114 # the piobus a direct connection to physical memory
115 #
116 self.piobus.port = physmem.port
117
118 self.disk0 = CowIdeDisk(driveID='master')
119 self.disk2 = CowIdeDisk(driveID='master')
120 self.disk0.childImage(mdesc.disk())
121 self.disk2.childImage(disk('linux-bigswap2.img'))
122 self.tsunami = BaseTsunami()
123 self.tsunami.attachIO(self.piobus)
124 self.tsunami.ide.pio = self.piobus.port
125 self.tsunami.ethernet.pio = self.piobus.port
126
127 #
128 # Store the dma devices for later connection to dma ruby ports.
129 # Append an underscore to dma_devices to avoid the SimObjectVector check.
130 #
131 self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
132
133 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
134 read_only = True))
135 self.intrctrl = IntrControl()
136 self.mem_mode = mem_mode
137 self.terminal = Terminal()
138 self.kernel = binary('vmlinux')
139 self.pal = binary('ts_osfpal')
140 self.console = binary('console')
141 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
142
143 return self
144
145def makeSparcSystem(mem_mode, mdesc = None):
146 class CowMmDisk(MmDisk):
147 image = CowDiskImage(child=RawDiskImage(read_only=True),
148 read_only=False)
149
150 def childImage(self, ci):
151 self.image.child.image_file = ci
152
153 self = SparcSystem()
154 if not mdesc:
155 # generic system
156 mdesc = SysConfig()
157 self.readfile = mdesc.script()
158 self.iobus = Bus(bus_id=0)
159 self.membus = MemBus(bus_id=1)
160 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
161 self.t1000 = T1000()
162 self.t1000.attachOnChipIO(self.membus)
163 self.t1000.attachIO(self.iobus)
164 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
165 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
166 self.bridge.side_a = self.iobus.port
167 self.bridge.side_b = self.membus.port
168 self.physmem.port = self.membus.port
169 self.physmem2.port = self.membus.port
170 self.rom.port = self.membus.port
171 self.nvram.port = self.membus.port
172 self.hypervisor_desc.port = self.membus.port
173 self.partition_desc.port = self.membus.port
174 self.intrctrl = IntrControl()
175 self.disk0 = CowMmDisk()
176 self.disk0.childImage(disk('disk.s10hw2'))
177 self.disk0.pio = self.iobus.port
178 self.reset_bin = binary('reset_new.bin')
179 self.hypervisor_bin = binary('q_new.bin')
180 self.openboot_bin = binary('openboot_new.bin')
181 self.nvram_bin = binary('nvram1')
182 self.hypervisor_desc_bin = binary('1up-hv.bin')
183 self.partition_desc_bin = binary('1up-md.bin')
184
185 return self
186
187def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
188 assert machine_type
189
190 if bare_metal:
191 self = ArmSystem()
192 else:
193 self = LinuxArmSystem()
194
195 if not mdesc:
196 # generic system
197 mdesc = SysConfig()
198
199 self.readfile = mdesc.script()
200 self.iobus = Bus(bus_id=0)
201 self.membus = MemBus(bus_id=1)
202 self.membus.badaddr_responder.warn_access = "warn"
203 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
204 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
205 self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
206 file = disk('ael-arm.ext2'))
207 self.bridge.side_a = self.iobus.port
208 self.bridge.side_b = self.membus.port
209 self.physmem.port = self.membus.port
210 self.diskmem.port = self.membus.port
211
212 self.mem_mode = mem_mode
213
214 #self.cf0 = CowIdeDisk(driveID='master')
215 #self.cf0.childImage(mdesc.disk())
216 #self.cf_ctrl = IdeController(disks=[self.cf0],
217 # pci_func = 0, pci_dev = 0, pci_bus = 0,
218 # io_shift = 1, ctrl_offset = 2, Command = 0x1,
219 # BAR0 = 0x18000000, BAR0Size = '16B',
220 # BAR1 = 0x18000100, BAR1Size = '1B',
221 # BAR0LegacyIO = True, BAR1LegacyIO = True,)
222 #self.cf_ctrl.pio = self.iobus.port
223
224 if machine_type == "RealView_PBX":
225 self.realview = RealViewPBX()
226 elif machine_type == "RealView_EB":
227 self.realview = RealViewEB()
228 else:
229 print "Unknown Machine Type"
230 sys.exit(1)
231
232 if bare_metal:
233 # EOT character on UART will end the simulation
234 self.realview.uart.end_on_eot = True
235 else:
236 self.machine_type = machine_type
237 self.kernel = binary('vmlinux.arm')
238 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' + \
239 ' lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000' + \
240 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
241
242 self.realview.attachOnChipIO(self.membus)
243 self.realview.attachIO(self.iobus)
244
245 self.intrctrl = IntrControl()
246 self.terminal = Terminal()
247 self.vncserver = VncServer()
248
249 return self
250
251
252def makeLinuxMipsSystem(mem_mode, mdesc = None):
253 class BaseMalta(Malta):
254 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
255 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
256 pci_func=0, pci_dev=0, pci_bus=0)
257
258 self = LinuxMipsSystem()
259 if not mdesc:
260 # generic system
261 mdesc = SysConfig()
262 self.readfile = mdesc.script()
263 self.iobus = Bus(bus_id=0)
264 self.membus = MemBus(bus_id=1)
265 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
266 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
267 self.bridge.side_a = self.iobus.port
268 self.bridge.side_b = self.membus.port
269 self.physmem.port = self.membus.port
270 self.disk0 = CowIdeDisk(driveID='master')
271 self.disk2 = CowIdeDisk(driveID='master')
272 self.disk0.childImage(mdesc.disk())
273 self.disk2.childImage(disk('linux-bigswap2.img'))
274 self.malta = BaseMalta()
275 self.malta.attachIO(self.iobus)
276 self.malta.ide.pio = self.iobus.port
277 self.malta.ethernet.pio = self.iobus.port
278 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
279 read_only = True))
280 self.intrctrl = IntrControl()
281 self.mem_mode = mem_mode
282 self.terminal = Terminal()
283 self.kernel = binary('mips/vmlinux')
284 self.console = binary('mips/console')
285 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
286
287 return self
288
289def x86IOAddress(port):
290 IO_address_space_base = 0x8000000000000000
291 return IO_address_space_base + port;
292
293def connectX86ClassicSystem(x86_sys):
294 x86_sys.membus = MemBus(bus_id=1)
295 x86_sys.physmem.port = x86_sys.membus.port
296
297 # North Bridge
298 x86_sys.iobus = Bus(bus_id=0)
299 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
300 x86_sys.bridge.side_a = x86_sys.iobus.port
301 x86_sys.bridge.side_b = x86_sys.membus.port
302
303 # connect the io bus
304 x86_sys.pc.attachIO(x86_sys.iobus)
305
306def connectX86RubySystem(x86_sys):
307 # North Bridge
308 x86_sys.piobus = Bus(bus_id=0)
309
310 #
311 # Pio functional accesses from devices need direct access to memory
312 # RubyPort currently does support functional accesses. Therefore provide
313 # the piobus a direct connection to physical memory
314 #
315 x86_sys.piobus.port = x86_sys.physmem.port
316
317 x86_sys.pc.attachIO(x86_sys.piobus)
318
319
320def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
321 if self == None:
322 self = X86System()
323
324 if not mdesc:
325 # generic system
326 mdesc = SysConfig()
327 self.readfile = mdesc.script()
328
329 self.mem_mode = mem_mode
330
331 # Physical memory
332 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
333
334 # Platform
335 self.pc = Pc()
336
337 # Create and connect the busses required by each memory system
338 if Ruby:
339 connectX86RubySystem(self)
340 # add the ide to the list of dma devices that later need to attach to
341 # dma controllers
342 self._dma_devices = [self.pc.south_bridge.ide]
343 else:
344 connectX86ClassicSystem(self)
345
346 self.intrctrl = IntrControl()
347
348 # Disks
349 disk0 = CowIdeDisk(driveID='master')
350 disk2 = CowIdeDisk(driveID='master')
351 disk0.childImage(mdesc.disk())
352 disk2.childImage(disk('linux-bigswap2.img'))
353 self.pc.south_bridge.ide.disks = [disk0, disk2]
354
355 # Add in a Bios information structure.
356 structures = [X86SMBiosBiosInformation()]
357 self.smbios_table.structures = structures
358
359 # Set up the Intel MP table
360 for i in xrange(numCPUs):
361 bp = X86IntelMPProcessor(
362 local_apic_id = i,
363 local_apic_version = 0x14,
364 enable = True,
365 bootstrap = (i == 0))
366 self.intel_mp_table.add_entry(bp)
367 io_apic = X86IntelMPIOAPIC(
368 id = numCPUs,
369 version = 0x11,
370 enable = True,
371 address = 0xfec00000)
372 self.pc.south_bridge.io_apic.apic_id = io_apic.id
373 self.intel_mp_table.add_entry(io_apic)
374 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
375 self.intel_mp_table.add_entry(isa_bus)
376 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
377 self.intel_mp_table.add_entry(pci_bus)
378 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
379 subtractive_decode=True, parent_bus=1)
380 self.intel_mp_table.add_entry(connect_busses)
381 pci_dev4_inta = X86IntelMPIOIntAssignment(
382 interrupt_type = 'INT',
383 polarity = 'ConformPolarity',
384 trigger = 'ConformTrigger',
385 source_bus_id = 1,
386 source_bus_irq = 0 + (4 << 2),
387 dest_io_apic_id = io_apic.id,
388 dest_io_apic_intin = 16)
389 self.intel_mp_table.add_entry(pci_dev4_inta);
390 def assignISAInt(irq, apicPin):
391 assign_8259_to_apic = X86IntelMPIOIntAssignment(
392 interrupt_type = 'ExtInt',
393 polarity = 'ConformPolarity',
394 trigger = 'ConformTrigger',
395 source_bus_id = 0,
396 source_bus_irq = irq,
397 dest_io_apic_id = io_apic.id,
398 dest_io_apic_intin = 0)
399 self.intel_mp_table.add_entry(assign_8259_to_apic)
400 assign_to_apic = X86IntelMPIOIntAssignment(
401 interrupt_type = 'INT',
402 polarity = 'ConformPolarity',
403 trigger = 'ConformTrigger',
404 source_bus_id = 0,
405 source_bus_irq = irq,
406 dest_io_apic_id = io_apic.id,
407 dest_io_apic_intin = apicPin)
408 self.intel_mp_table.add_entry(assign_to_apic)
409 assignISAInt(0, 2)
410 assignISAInt(1, 1)
411 for i in range(3, 15):
412 assignISAInt(i, i)
413
414def setWorkCountOptions(system, options):
415 if options.work_item_id != None:
416 system.work_item_id = options.work_item_id
417 if options.work_begin_cpu_id_exit != None:
418 system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
419 if options.work_end_exit_count != None:
420 system.work_end_exit_count = options.work_end_exit_count
421 if options.work_end_checkpoint_count != None:
422 system.work_end_ckpt_count = options.work_end_checkpoint_count
423 if options.work_begin_exit_count != None:
424 system.work_begin_exit_count = options.work_begin_exit_count
425 if options.work_begin_checkpoint_count != None:
426 system.work_begin_ckpt_count = options.work_begin_checkpoint_count
427 if options.work_cpus_checkpoint_count != None:
428 system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
429
430
431def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
432 self = LinuxX86System()
433
434 # Build up the x86 system and then specialize it for Linux
435 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
436
437 # We assume below that there's at least 1MB of memory. We'll require 2
438 # just to avoid corner cases.
439 assert(self.physmem.range.second.getValue() >= 0x200000)
440
441 # Mark the first megabyte of memory as reserved
442 self.e820_table.entries.append(X86E820Entry(
443 addr = 0,
444 size = '1MB',
445 range_type = 2))
446
447 # Mark the rest as available
448 self.e820_table.entries.append(X86E820Entry(
449 addr = 0x100000,
450 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
451 range_type = 1))
452
453 # Command line
454 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
455 'root=/dev/hda1'
456 return self
457
458
459def makeDualRoot(testSystem, driveSystem, dumpfile):
460 self = Root()
461 self.testsys = testSystem
462 self.drivesys = driveSystem
463 self.etherlink = EtherLink()
464 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
465 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
466
467 if dumpfile:
468 self.etherdump = EtherDump(file=dumpfile)
469 self.etherlink.dump = Parent.etherdump
470
471 return self
472
473def setMipsOptions(TestCPUClass):
474 #CP0 Configuration
475 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
476 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
477 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
478 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
479
480 #CP0 Interrupt Control
481 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
482 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
483
484 # Config Register
485 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
486 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
487 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
488 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
489 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
490 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
491 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
492
493 #Config 1 Register
494 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
495 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
496 # ***VERY IMPORTANT***
497 # Remember to modify CP0_Config1 according to cache specs
498 # Examine file ../common/Cache.py
499 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
500 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
501 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
502 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
503 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
504 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
505 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
506 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
507 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
508 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
509 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
510 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
511 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
512
513 #Config 2 Register
514 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
515 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
516 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
517 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
518 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
519 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
520 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
521 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
522 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
523
524
525 #Config 3 Register
526 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
527 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
528 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
529 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
530 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
531 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
532 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
533 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
534 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
535
536 #SRS Ctl - HSS
537 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
538
539
540 #TestCPUClass.CoreParams.tlb = TLB()
541 #TestCPUClass.CoreParams.UnifiedTLB = 1