1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46class CowIdeDisk(IdeDisk):
47 image = CowDiskImage(child=RawDiskImage(read_only=True),
48 read_only=False)
49
50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
59
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70
71 self.tsunami = BaseTsunami()
72
73 # Create the io bus to connect all device ports
74 self.iobus = NoncoherentBus()
75 self.tsunami.attachIO(self.iobus)
76
77 self.tsunami.ide.pio = self.iobus.master
78 self.tsunami.ide.config = self.iobus.master
79
80 self.tsunami.ethernet.pio = self.iobus.master
81 self.tsunami.ethernet.config = self.iobus.master
82
83 if ruby:
84 # Store the dma devices for later connection to dma ruby ports.
85 # Append an underscore to dma_ports to avoid the SimObjectVector check.
86 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
87 else:
88 self.membus = MemBus()
89
90 # By default the bridge responds to all addresses above the I/O
91 # base address (including the PCI config space)
92 IO_address_space_base = 0x80000000000
93 self.bridge = Bridge(delay='50ns',
94 ranges = [AddrRange(IO_address_space_base, Addr.max)])
95 self.bridge.master = self.iobus.slave
96 self.bridge.slave = self.membus.master
97
98 self.tsunami.ide.dma = self.iobus.slave
99 self.tsunami.ethernet.dma = self.iobus.slave
100
101 self.system_port = self.membus.slave
102
103 self.mem_ranges = [AddrRange(mdesc.mem())]
104 self.disk0 = CowIdeDisk(driveID='master')
105 self.disk2 = CowIdeDisk(driveID='master')
106 self.disk0.childImage(mdesc.disk())
107 self.disk2.childImage(disk('linux-bigswap2.img'))
108 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
109 read_only = True))
110 self.intrctrl = IntrControl()
111 self.mem_mode = mem_mode
112 self.terminal = Terminal()
113 self.kernel = binary('vmlinux')
114 self.pal = binary('ts_osfpal')
115 self.console = binary('console')
116 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
117
118 return self
119
120def makeSparcSystem(mem_mode, mdesc = None):
121 # Constants from iob.cc and uart8250.cc
122 iob_man_addr = 0x9800000000
123 uart_pio_size = 8
124
125 class CowMmDisk(MmDisk):
126 image = CowDiskImage(child=RawDiskImage(read_only=True),
127 read_only=False)
128
129 def childImage(self, ci):
130 self.image.child.image_file = ci
131
132 self = SparcSystem()
133 if not mdesc:
134 # generic system
135 mdesc = SysConfig()
136 self.readfile = mdesc.script()
137 self.iobus = NoncoherentBus()
138 self.membus = MemBus()
139 self.bridge = Bridge(delay='50ns')
140 self.t1000 = T1000()
141 self.t1000.attachOnChipIO(self.membus)
142 self.t1000.attachIO(self.iobus)
143 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
144 AddrRange(Addr('2GB'), size ='256MB')]
145 self.bridge.master = self.iobus.slave
146 self.bridge.slave = self.membus.master
147 self.rom.port = self.membus.master
148 self.nvram.port = self.membus.master
149 self.hypervisor_desc.port = self.membus.master
150 self.partition_desc.port = self.membus.master
151 self.intrctrl = IntrControl()
152 self.disk0 = CowMmDisk()
153 self.disk0.childImage(disk('disk.s10hw2'))
154 self.disk0.pio = self.iobus.master
155
156 # The puart0 and hvuart are placed on the IO bus, so create ranges
157 # for them. The remaining IO range is rather fragmented, so poke
158 # holes for the iob and partition descriptors etc.
159 self.bridge.ranges = \
160 [
161 AddrRange(self.t1000.puart0.pio_addr,
162 self.t1000.puart0.pio_addr + uart_pio_size - 1),
163 AddrRange(self.disk0.pio_addr,
164 self.t1000.fake_jbi.pio_addr +
165 self.t1000.fake_jbi.pio_size - 1),
166 AddrRange(self.t1000.fake_clk.pio_addr,
167 iob_man_addr - 1),
168 AddrRange(self.t1000.fake_l2_1.pio_addr,
169 self.t1000.fake_ssi.pio_addr +
170 self.t1000.fake_ssi.pio_size - 1),
171 AddrRange(self.t1000.hvuart.pio_addr,
172 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
173 ]
174 self.reset_bin = binary('reset_new.bin')
175 self.hypervisor_bin = binary('q_new.bin')
176 self.openboot_bin = binary('openboot_new.bin')
177 self.nvram_bin = binary('nvram1')
178 self.hypervisor_desc_bin = binary('1up-hv.bin')
179 self.partition_desc_bin = binary('1up-md.bin')
180
181 self.system_port = self.membus.slave
182
183 return self
184
185def makeArmSystem(mem_mode, machine_type, mdesc = None,
186 dtb_filename = None, bare_metal=False):
187 assert machine_type
188
189 if bare_metal:
190 self = ArmSystem()
191 else:
192 self = LinuxArmSystem()
193
194 if not mdesc:
195 # generic system
196 mdesc = SysConfig()
197
198 self.readfile = mdesc.script()
199 self.iobus = NoncoherentBus()
200 self.membus = MemBus()
201 self.membus.badaddr_responder.warn_access = "warn"
202 self.bridge = Bridge(delay='50ns')
203 self.bridge.master = self.iobus.slave
204 self.bridge.slave = self.membus.master
205
206 self.mem_mode = mem_mode
207
208 if machine_type == "RealView_PBX":
209 self.realview = RealViewPBX()
210 elif machine_type == "RealView_EB":
211 self.realview = RealViewEB()
212 elif machine_type == "VExpress_ELT":
213 self.realview = VExpress_ELT()
214 elif machine_type == "VExpress_EMM":
215 self.realview = VExpress_EMM()
216 elif machine_type == "VExpress_EMM64":
217 self.realview = VExpress_EMM64()
218 else:
219 print "Unknown Machine Type"
220 sys.exit(1)
221
222 self.cf0 = CowIdeDisk(driveID='master')
223 self.cf0.childImage(mdesc.disk())
224
225 # Attach any PCI devices this platform supports
226 self.realview.attachPciDevices()
227 # default to an IDE controller rather than a CF one
228 # assuming we've got one; EMM64 is an exception for the moment
229 if machine_type != "VExpress_EMM64":
230 try:
231 self.realview.ide.disks = [self.cf0]
232 except:
233 self.realview.cf_ctrl.disks = [self.cf0]
234 else:
235 self.realview.cf_ctrl.disks = [self.cf0]
236
237 if bare_metal:
238 # EOT character on UART will end the simulation
239 self.realview.uart.end_on_eot = True
240 self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
241 size = mdesc.mem())]
242 else:
243 if machine_type == "VExpress_EMM64":
244 self.kernel = binary('vmlinux-3.14-aarch64-vexpress-emm64')
245 elif machine_type == "VExpress_EMM":
246 self.kernel = binary('vmlinux-3.3-arm-vexpress-emm-pcie')
247 else:
248 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
249
250 if dtb_filename:
251 self.dtb_filename = binary(dtb_filename)
252 self.machine_type = machine_type
253 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
254 print "The currently selected ARM platforms doesn't support"
255 print " the amount of DRAM you've selected. Please try"
256 print " another platform"
257 sys.exit(1)
258
259 # Ensure that writes to the UART actually go out early in the boot
260 boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
261 'lpj=19988480 norandmaps rw loglevel=8 ' + \
262 'mem=%s root=/dev/sda1' % mdesc.mem()
263
264 self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
265 size = mdesc.mem())]
266 self.realview.setupBootLoader(self.membus, self, binary)
267 self.gic_cpu_addr = self.realview.gic.cpu_addr
268 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
269
270 if mdesc.disk().lower().count('android'):
271 boot_flags += " init=/init "
272 self.boot_osflags = boot_flags
273 self.realview.attachOnChipIO(self.membus, self.bridge)
274 self.realview.attachIO(self.iobus)
275 self.intrctrl = IntrControl()
276 self.terminal = Terminal()
277 self.vncserver = VncServer()
278
279 self.system_port = self.membus.slave
280
281 return self
282
283
284def makeLinuxMipsSystem(mem_mode, mdesc = None):
285 class BaseMalta(Malta):
286 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
287 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
288 pci_func=0, pci_dev=0, pci_bus=0)
289
290 self = LinuxMipsSystem()
291 if not mdesc:
292 # generic system
293 mdesc = SysConfig()
294 self.readfile = mdesc.script()
295 self.iobus = NoncoherentBus()
296 self.membus = MemBus()
297 self.bridge = Bridge(delay='50ns')
298 self.mem_ranges = [AddrRange('1GB')]
299 self.bridge.master = self.iobus.slave
300 self.bridge.slave = self.membus.master
301 self.disk0 = CowIdeDisk(driveID='master')
302 self.disk2 = CowIdeDisk(driveID='master')
303 self.disk0.childImage(mdesc.disk())
304 self.disk2.childImage(disk('linux-bigswap2.img'))
305 self.malta = BaseMalta()
306 self.malta.attachIO(self.iobus)
307 self.malta.ide.pio = self.iobus.master
308 self.malta.ide.config = self.iobus.master
309 self.malta.ide.dma = self.iobus.slave
310 self.malta.ethernet.pio = self.iobus.master
311 self.malta.ethernet.config = self.iobus.master
312 self.malta.ethernet.dma = self.iobus.slave
313 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
314 read_only = True))
315 self.intrctrl = IntrControl()
316 self.mem_mode = mem_mode
317 self.terminal = Terminal()
318 self.kernel = binary('mips/vmlinux')
319 self.console = binary('mips/console')
320 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
321
322 self.system_port = self.membus.slave
323
324 return self
325
326def x86IOAddress(port):
327 IO_address_space_base = 0x8000000000000000
328 return IO_address_space_base + port
329
330def connectX86ClassicSystem(x86_sys, numCPUs):
331 # Constants similar to x86_traits.hh
332 IO_address_space_base = 0x8000000000000000
333 pci_config_address_space_base = 0xc000000000000000
334 interrupts_address_space_base = 0xa000000000000000
335 APIC_range_size = 1 << 12;
336
337 x86_sys.membus = MemBus()
338
339 # North Bridge
340 x86_sys.iobus = NoncoherentBus()
341 x86_sys.bridge = Bridge(delay='50ns')
342 x86_sys.bridge.master = x86_sys.iobus.slave
343 x86_sys.bridge.slave = x86_sys.membus.master
344 # Allow the bridge to pass through the IO APIC (two pages),
345 # everything in the IO address range up to the local APIC, and
346 # then the entire PCI address space and beyond
347 x86_sys.bridge.ranges = \
348 [
349 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
350 x86_sys.pc.south_bridge.io_apic.pio_addr +
351 APIC_range_size - 1),
352 AddrRange(IO_address_space_base,
353 interrupts_address_space_base - 1),
354 AddrRange(pci_config_address_space_base,
355 Addr.max)
356 ]
357
358 # Create a bridge from the IO bus to the memory bus to allow access to
359 # the local APIC (two pages)
360 x86_sys.apicbridge = Bridge(delay='50ns')
361 x86_sys.apicbridge.slave = x86_sys.iobus.master
362 x86_sys.apicbridge.master = x86_sys.membus.slave
363 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
364 interrupts_address_space_base +
365 numCPUs * APIC_range_size
366 - 1)]
367
368 # connect the io bus
369 x86_sys.pc.attachIO(x86_sys.iobus)
370
371 x86_sys.system_port = x86_sys.membus.slave
372
373def connectX86RubySystem(x86_sys):
374 # North Bridge
375 x86_sys.iobus = NoncoherentBus()
376
377 # add the ide to the list of dma devices that later need to attach to
378 # dma controllers
379 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
380 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
381
382
383def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
384 Ruby = False):
385 if self == None:
386 self = X86System()
387
388 if not mdesc:
389 # generic system
390 mdesc = SysConfig()
391 self.readfile = mdesc.script()
392
393 self.mem_mode = mem_mode
394
395 # Physical memory
396 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
397 # for various devices. Hence, if the physical memory size is greater than
398 # 3GB, we need to split it into two parts.
399 excess_mem_size = \
400 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
401 if excess_mem_size <= 0:
402 self.mem_ranges = [AddrRange(mdesc.mem())]
403 else:
404 warn("Physical memory size specified is %s which is greater than " \
405 "3GB. Twice the number of memory controllers would be " \
406 "created." % (mdesc.mem()))
407
408 self.mem_ranges = [AddrRange('3GB'),
409 AddrRange(Addr('4GB'), size = excess_mem_size)]
410
411 # Platform
412 self.pc = Pc()
413
414 # Create and connect the busses required by each memory system
415 if Ruby:
416 connectX86RubySystem(self)
417 else:
418 connectX86ClassicSystem(self, numCPUs)
419
420 self.intrctrl = IntrControl()
421
422 # Disks
423 disk0 = CowIdeDisk(driveID='master')
424 disk2 = CowIdeDisk(driveID='master')
425 disk0.childImage(mdesc.disk())
426 disk2.childImage(disk('linux-bigswap2.img'))
427 self.pc.south_bridge.ide.disks = [disk0, disk2]
428
429 # Add in a Bios information structure.
430 structures = [X86SMBiosBiosInformation()]
431 self.smbios_table.structures = structures
432
433 # Set up the Intel MP table
434 base_entries = []
435 ext_entries = []
436 for i in xrange(numCPUs):
437 bp = X86IntelMPProcessor(
438 local_apic_id = i,
439 local_apic_version = 0x14,
440 enable = True,
441 bootstrap = (i == 0))
442 base_entries.append(bp)
443 io_apic = X86IntelMPIOAPIC(
444 id = numCPUs,
445 version = 0x11,
446 enable = True,
447 address = 0xfec00000)
448 self.pc.south_bridge.io_apic.apic_id = io_apic.id
449 base_entries.append(io_apic)
450 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
451 base_entries.append(isa_bus)
452 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
453 base_entries.append(pci_bus)
454 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
455 subtractive_decode=True, parent_bus=1)
456 ext_entries.append(connect_busses)
457 pci_dev4_inta = X86IntelMPIOIntAssignment(
458 interrupt_type = 'INT',
459 polarity = 'ConformPolarity',
460 trigger = 'ConformTrigger',
461 source_bus_id = 1,
462 source_bus_irq = 0 + (4 << 2),
463 dest_io_apic_id = io_apic.id,
464 dest_io_apic_intin = 16)
465 base_entries.append(pci_dev4_inta)
466 def assignISAInt(irq, apicPin):
467 assign_8259_to_apic = X86IntelMPIOIntAssignment(
468 interrupt_type = 'ExtInt',
469 polarity = 'ConformPolarity',
470 trigger = 'ConformTrigger',
471 source_bus_id = 0,
472 source_bus_irq = irq,
473 dest_io_apic_id = io_apic.id,
474 dest_io_apic_intin = 0)
475 base_entries.append(assign_8259_to_apic)
476 assign_to_apic = X86IntelMPIOIntAssignment(
477 interrupt_type = 'INT',
478 polarity = 'ConformPolarity',
479 trigger = 'ConformTrigger',
480 source_bus_id = 0,
481 source_bus_irq = irq,
482 dest_io_apic_id = io_apic.id,
483 dest_io_apic_intin = apicPin)
484 base_entries.append(assign_to_apic)
485 assignISAInt(0, 2)
486 assignISAInt(1, 1)
487 for i in range(3, 15):
488 assignISAInt(i, i)
489 self.intel_mp_table.base_entries = base_entries
490 self.intel_mp_table.ext_entries = ext_entries
491
492def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
493 Ruby = False):
494 self = LinuxX86System()
495
496 # Build up the x86 system and then specialize it for Linux
497 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
498
499 # We assume below that there's at least 1MB of memory. We'll require 2
500 # just to avoid corner cases.
501 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
502 assert(phys_mem_size >= 0x200000)
503 assert(len(self.mem_ranges) <= 2)
504
505 entries = \
506 [
507 # Mark the first megabyte of memory as reserved
508 X86E820Entry(addr = 0, size = '639kB', range_type = 1),
509 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
510 # Mark the rest of physical memory as available
511 X86E820Entry(addr = 0x100000,
512 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
513 range_type = 1),
514 # Reserve the last 16kB of the 32-bit address space for the
515 # m5op interface
516 X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
517 ]
518
519 # In case the physical memory is greater than 3GB, we split it into two
520 # parts and add a separate e820 entry for the second part. This entry
521 # starts at 0x100000000, which is the first address after the space
522 # reserved for devices.
523 if len(self.mem_ranges) == 2:
524 entries.append(X86E820Entry(addr = 0x100000000,
525 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
526
527 self.e820_table.entries = entries
528
529 # Command line
530 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
531 'root=/dev/hda1'
532 self.kernel = binary('x86_64-vmlinux-2.6.22.9')
533 return self
534
535
536def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
537 self = Root(full_system = full_system)
538 self.testsys = testSystem
539 self.drivesys = driveSystem
540 self.etherlink = EtherLink()
541
542 if hasattr(testSystem, 'realview'):
543 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
544 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
545 elif hasattr(testSystem, 'tsunami'):
546 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
547 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
548 else:
549 fatal("Don't know how to connect these system together")
550
551 if dumpfile:
552 self.etherdump = EtherDump(file=dumpfile)
553 self.etherlink.dump = Parent.etherdump
554
555 return self