Searched refs:tcr (Results 1 - 4 of 4) sorted by relevance
/gem5/src/arch/arm/ |
H A D | utility.cc | 386 TTBCR tcr) 391 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) 393 else if (!bits(addr, 55, 48) && tcr.tbi0) 398 tcr = tc->readMiscReg(MISCREG_TCR_EL2); 399 if (tcr.tbi) 404 if (tcr.tbi) 418 TTBCR tcr; local 423 tcr = tc->readMiscReg(MISCREG_TCR_EL1); 424 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) 426 else if (!bits(addr, 55, 48) && tcr 385 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TTBCR tcr) argument [all...] |
H A D | table_walker.cc | 134 sctlr(0), scr(0), cpsr(0), tcr(0), 275 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); 280 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); 285 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3); 744 currState->vaddr_tainted, currState->tcr); 789 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); 790 tg = GrainMap_tg0[currState->tcr.tg0]; 791 currState->hpd = currState->tcr.hpd0; 793 currState->tcr.epd0) 799 tsz = adjustTableSizeAArch64(64 - currState->tcr [all...] |
H A D | utility.hh | 233 TTBCR tcr);
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H A D | table_walker.hh | 735 /** Cached copy of ttbcr/tcr as it existed when translation began */ 738 TCR tcr; // AArch64 translations member in union:ArmISA::TableWalker::LongDescriptor::WalkerState::__anon1
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