Searched refs:counters (Results 1 - 8 of 8) sorted by relevance

/gem5/ext/drampower/src/libdrampower/
H A DLibDRAMPower.cc48 counters(memSpec),
58 counters(CommandAnalysis(memSpec)),
76 counters.getCommands(cmdList, lastUpdate, timestamp);
83 mpm.power_calc(memSpec, counters, includeIoAndTermination, bwPowerParams);
90 mpm.power_calc(memSpec, counters, includeIoAndTermination, bwPowerParams);
97 counters.clear();
102 counters.clearStats(timestamp);
H A DLibDRAMPower.h82 Data::CommandAnalysis counters; member in class:libDRAMPower
/gem5/ext/drampower/src/
H A DTraceParser.cc46 counters(memSpec)
83 counters = CommandAnalysis(memSpec);
96 counters.getCommands(cmd_list, lastupdate);
102 counters.getCommands(cmd_list, lastupdate);
112 counters.getCommands(cmd_list, lastupdate);
118 counters.getCommands(cmd_list, lastupdate);
121 counters.clear();
H A DTraceParser.h58 Data::CommandAnalysis counters; member in class:TraceParser
/gem5/ext/drampower/test/libdrampowertest/
H A Dlib_test.cc117 std::cout << "Number of ACTs: " << std::accumulate(test.counters.numberofactsBanks.begin(),
118 test.counters.numberofactsBanks.end()
120 std::cout << "Number of RDs: " << std::accumulate(test.counters.numberofreadsBanks.begin(),
121 test.counters.numberofreadsBanks.end()
123 std::cout << "Number of PREs: " << std::accumulate(test.counters.numberofpresBanks.begin(),
124 test.counters.numberofpresBanks.end()
/gem5/src/arch/arm/
H A Dpmu.hh88 * In order to support CPU switching and some combined counters (e.g.,
149 // Number of event counters implemented
205 * changes PMU-global state (e.g., resets all counters).
212 * Reset all event counters excluding the cycle counter to zero.
231 * counters are treated as constant '0'.
245 * non-existing counters are ignored.
254 * performance counter or the cycle counter. Non-existing counters
269 * non-existing counters are ignored. The method automatically
316 * notify an event increment of val units, all the attached counters'
342 /** set of counters usin
603 std::vector<CounterState> counters; member in class:ArmISA::PMU
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H A Dpmu.cc75 fatal("The PMU can only accept 31 counters, %d counters requested.\n",
173 // Re-attach enabled counters after a resume in case they changed.
182 // counters can be configured
184 counters.emplace_back(*this, index);
429 for (int i = 0; i < counters.size(); ++i) {
430 CounterState &ctr(counters[i]);
598 for (CounterState &ctr : counters)
705 for (size_t i = 0; i < counters.size(); ++i)
706 counters[
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/gem5/util/streamline/
H A Dm5stats2streamline.py864 # Streamline counters are organized per CPU
1027 counters = ET.SubElement(xml, "counters")
1029 s = ET.SubElement(counters, "counter")
1095 # Writes selected gem5 statistics as Streamline counters

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