/gem5/tests/configs/ |
H A D | checkpoint.py | 78 cause = e.getCause() 79 if cause in _exit_limit: 82 elif cause in _exit_normal: 85 print("Test failed: Unknown exit cause: %s" % cause) 129 cause = e.getCause() 130 if cause in _exit_normal: 133 print("Test failed: Unknown exit cause: %s" % cause)
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/gem5/src/sim/ |
H A D | sim_events.cc | 61 cause(_cause), code(c), repeat(r) 68 cause(_cause), code(c), repeat(r) 110 cause(_cause), code(c), repeat(r) 120 exitSimLoop(cause, 0); 135 SERIALIZE_SCALAR(cause); 145 UNSERIALIZE_SCALAR(cause); 154 : Event(Sim_Exit_Pri), cause(_cause), downCounter(counter) 168 exitSimLoop(cause, 0);
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H A D | sim_events.hh | 58 std::string cause; member in class:GlobalSimLoopExitEvent 67 const std::string getCause() const { return cause; } 79 std::string cause; member in class:LocalSimLoopExitEvent 87 const std::string getCause() const { return cause; } 106 std::string cause; // string explaining why we're terminating member in class:CountedExitEvent
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/gem5/src/arch/mips/ |
H A D | interrupts.cc | 47 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local 48 return cause.ip; 53 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local 54 cause.ip = val; 55 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 123 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local 124 if (status.im && cause.ip) 138 CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local 140 (unsigned)status.im, (unsigned)cause.ip);
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H A D | faults.cc | 127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); local 128 cause.excCode = excCode; 129 cause.bd = delay_slot ? 1 : 0; 130 cause.ce = 0; 131 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
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H A D | remote_gdb.hh | 62 uint32_t cause; member in struct:MipsISA::RemoteGDB::MipsGdbRegCache::__anon4
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H A D | remote_gdb.cc | 181 r.cause = context->readMiscRegNoEffect(MISCREG_CAUSE); 198 context->setMiscRegNoEffect(MISCREG_CAUSE, r.cause);
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H A D | faults.hh | 170 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); local 171 cause.ce = coProcID; 172 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 183 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); local 185 return cause.iv ? 0x200 : 0x180;
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/gem5/util/systemc/systemc_within_gem5/systemc_simple_object/ |
H A D | config.py | 58 cause = m5.simulate(m5.MaxTick).getCause() variable 59 print(cause)
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/gem5/configs/example/ |
H A D | sc_main.py | 44 cause = m5.simulate(m5.MaxTick).getCause() variable
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/gem5/src/systemc/tests/ |
H A D | config.py | 47 cause = m5.simulate(m5.MaxTick).getCause() variable
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H A D | verify.py | 360 def failed(self, test, cause, note=''): 362 self._failed.setdefault(cause, []).append(test) 375 cause: map(lambda t: t.props, tests) for 376 cause, tests in self._failed.iteritems() 392 for cause, tests in sorted(self._failed.items()): 393 block = ' ' + cause.capitalize() + ':\n'
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/gem5/util/systemc/systemc_within_gem5/systemc_sc_main/ |
H A D | config.py | 64 cause = m5.simulate(m5.MaxTick).getCause() variable
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/gem5/tests/test-progs/asmtest/src/riscv/env/v/ |
H A D | vm.c | 123 void handle_fault(uintptr_t addr, uintptr_t cause) argument 132 assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT); 164 if (tf->cause == CAUSE_USER_ECALL) 173 else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) 186 else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT) 187 handle_fault(tf->badvaddr, tf->cause); 196 // cause coherence misses without affecting program semantics
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H A D | riscv_test.h | 67 long cause; member in struct:__anon74
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H A D | entry.S | 114 # get sr, epc, badvaddr, cause
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/gem5/src/arch/riscv/ |
H A D | faults.cc | 85 MiscRegIndex cause, epc, tvec, tval; local 88 cause = MISCREG_UCAUSE; 97 cause = MISCREG_SCAUSE; 107 cause = MISCREG_MCAUSE; 121 // Set fault cause, privilege, and return PC 122 tc->setMiscReg(cause,
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | mcsr.S | 26 # Check that reading the following CSRs doesn't cause an exception 31 # Check that writing hte following CSRs doesn't cause an exception
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/gem5/src/cpu/ |
H A D | base.cc | 169 const char *cause = "a thread reached the max instruction count"; local 171 scheduleInstStop(tid, p->max_insts_any_thread, cause); 179 const char *cause = "simpoint starting point found"; local 181 scheduleInstStop(0, p->simpoint_start_insts[i], cause); 185 const char *cause = "all threads reached the max instruction count"; local 193 Event *event = new CountedExitEvent(cause, *counter); 207 const char *cause = "a thread reached the max load count"; local 209 scheduleLoadStop(tid, p->max_loads_any_thread, cause); 213 const char *cause = "all threads reached the max load count"; local 220 Event *event = new CountedExitEvent(cause, *counte [all...] |
H A D | base.hh | 462 * @param cause Cause to signal in the exit event. 464 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 477 * @param cause Cause to signal in the exit event. 479 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
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/gem5/src/mem/cache/ |
H A D | base.hh | 968 /** The total number of cycles blocked for each blocked cause. */ 970 /** The number of times this cache blocked for each blocked cause. */ 973 /** The average number of cycles blocked for each blocked cause. */ 1130 * Marks the access path of the cache as blocked for the given cause. This 1132 * @param cause The reason for the cache blocking. 1134 void setBlocked(BlockedCause cause) argument 1136 uint8_t flag = 1 << cause; 1138 blocked_causes[cause]++; 1143 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocke 1153 clearBlocked(BlockedCause cause) argument [all...] |
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | ma_fetch.S | 131 # verify trap cause
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