/gem5/src/arch/x86/ |
H A D | emulenv.hh | 52 RegIndex reg; 53 RegIndex regm; 56 RegIndex index; 57 RegIndex base; 62 EmulEnv(RegIndex _reg, RegIndex _regm,
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/gem5/src/arch/alpha/ |
H A D | registers.hh | 75 const RegIndex ZeroReg = 31; // architecturally meaningful 77 const RegIndex StackPointerReg = 30; 78 const RegIndex GlobalPointerReg = 29; 79 const RegIndex ProcedureValueReg = 27; 80 const RegIndex ReturnAddressReg = 26; 81 const RegIndex ReturnValueReg = 0; 82 const RegIndex FramePointerReg = 15; 84 const RegIndex SyscallNumReg = 0; 85 const RegIndex FirstArgumentReg = 16; 86 const RegIndex SyscallPseudoReturnRe [all...] |
/gem5/src/arch/arm/insts/ |
H A D | macromem.hh | 115 RegIndex dest, ura; 120 RegIndex _dest, RegIndex _ura, uint32_t _imm) 134 RegIndex dest, op1; 138 RegIndex _dest, RegIndex _op1, uint32_t _step) 151 OpClass __opClass, RegIndex _dest, RegIndex _op1, 165 RegIndex dest, op1; 169 RegIndex _des [all...] |
H A D | macromem.cc | 460 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 461 unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 475 RegIndex rMid = deinterleave ? NumFloatV7ArchRegs : vd * 2; 556 RegIndex rn, RegIndex vd, unsigned regs, 558 RegIndex rm, unsigned lane) : 578 RegIndex ufp0 = NumFloatV7ArchRegs; 823 unsigned elems, RegIndex rn, RegIndex v [all...] |
H A D | static_inst.hh | 159 void printIntReg(std::ostream &os, RegIndex reg_idx, 161 void printFloatReg(std::ostream &os, RegIndex reg_idx) const; 162 void printVecReg(std::ostream &os, RegIndex reg_idx, 164 void printVecPredReg(std::ostream &os, RegIndex reg_idx) const; 165 void printCCReg(std::ostream &os, RegIndex reg_idx) const; 166 void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
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/gem5/src/cpu/ |
H A D | thread_context.hh | 209 virtual RegVal readIntReg(RegIndex reg_idx) const = 0; 211 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0; 251 virtual RegVal readCCReg(RegIndex reg_idx) const = 0; 253 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0; 255 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0; 264 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0; 286 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0; 288 virtual RegVal readMiscReg(RegIndex misc_reg) = 0; 290 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0; 292 virtual void setMiscReg(RegIndex misc_re [all...] |
H A D | simple_thread.hh | 285 readIntReg(RegIndex reg_idx) const override 296 readFloatReg(RegIndex reg_idx) const override 442 readCCReg(RegIndex reg_idx) const override 459 setIntReg(RegIndex reg_idx, RegVal val) override 469 setFloatReg(RegIndex reg_idx, RegVal val) override 512 setCCReg(RegIndex reg_idx, RegVal val) override 541 readMiscRegNoEffect(RegIndex misc_reg) const override 547 readMiscReg(RegIndex misc_reg) override 553 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 559 setMiscReg(RegIndex misc_re [all...] |
H A D | reg_class.hh | 83 RegIndex regIdx; 93 RegId(RegClass reg_class, RegIndex reg_idx) 96 explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx) 179 const RegIndex& index() const { return regIdx; } 180 RegIndex& index() { return regIdx; } 185 inline RegIndex flatIndex() const 204 const RegIndex& elemIndex() const { return elemIdx; } 365 const size_t shifted_class_num = class_num << (sizeof(RegIndex) << 3); 371 // If RegIndex is larger than size_t, then class_num will not be 374 static_assert(sizeof(RegIndex) < sizeo [all...] |
/gem5/src/cpu/o3/ |
H A D | thread_context.hh | 191 readReg(RegIndex reg_idx) 197 readIntReg(RegIndex reg_idx) const override 204 readFloatReg(RegIndex reg_idx) const override 305 readCCReg(RegIndex reg_idx) const override 313 setIntReg(RegIndex reg_idx, RegVal val) override 319 setFloatReg(RegIndex reg_idx, RegVal val) override 345 setCCReg(RegIndex reg_idx, RegVal val) override 385 readMiscRegNoEffect(RegIndex misc_reg) const override 393 readMiscReg(RegIndex misc_reg) override 399 void setMiscRegNoEffect(RegIndex misc_re [all...] |
H A D | thread_context_impl.hh | 208 O3ThreadContext<Impl>::readIntRegFlat(RegIndex reg_idx) const 215 O3ThreadContext<Impl>::readFloatRegFlat(RegIndex reg_idx) const 222 O3ThreadContext<Impl>::readVecRegFlat(RegIndex reg_id) const 229 O3ThreadContext<Impl>::getWritableVecRegFlat(RegIndex reg_id) 236 O3ThreadContext<Impl>::readVecElemFlat(RegIndex idx, 244 O3ThreadContext<Impl>::readVecPredRegFlat(RegIndex reg_id) const 251 O3ThreadContext<Impl>::getWritableVecPredRegFlat(RegIndex reg_id) 258 O3ThreadContext<Impl>::readCCRegFlat(RegIndex reg_idx) const 265 O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val) 274 O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_id [all...] |
H A D | rename_map.cc | 63 RegIndex _zeroReg) 113 RegIndex _intZeroReg, 114 RegIndex _floatZeroReg, 125 vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1); 128 &(freeList->vecElemList), (RegIndex)-1); 130 predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1); 132 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
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/gem5/src/arch/x86/insts/ |
H A D | microfpop.hh | 54 const RegIndex src1; 55 const RegIndex src2; 56 const RegIndex dest;
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H A D | microldstop.hh | 59 const RegIndex index; 60 const RegIndex base; 66 RegIndex foldOBit, foldABit; 97 const RegIndex data; 129 const RegIndex dataLow; 130 const RegIndex dataHi;
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H A D | microregop.hh | 53 const RegIndex src1; 54 const RegIndex dest; 57 RegIndex foldOBit; 82 const RegIndex src2;
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H A D | micromediaop.hh | 47 const RegIndex src1; 48 const RegIndex dest; 52 static const RegIndex foldOBit = 0; 94 const RegIndex src2;
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H A D | static_inst.hh | 56 explicit InstRegIndex(RegIndex _idx) : 64 RegClass computeRegClass(RegIndex _idx) { 104 uint8_t scale, RegIndex index, RegIndex base,
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H A D | static_inst.cc | 135 RegIndex reg_idx = reg.index(); 232 uint8_t scale, RegIndex index, RegIndex base,
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/gem5/src/cpu/checker/ |
H A D | thread_context.hh | 239 readIntReg(RegIndex reg_idx) const override 245 readFloatReg(RegIndex reg_idx) const override 341 readCCReg(RegIndex reg_idx) const override 347 setIntReg(RegIndex reg_idx, RegVal val) override 354 setFloatReg(RegIndex reg_idx, RegVal val) override 382 setCCReg(RegIndex reg_idx, RegVal val) override 425 readMiscRegNoEffect(RegIndex misc_reg) const override 431 readMiscReg(RegIndex misc_reg) override 437 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 446 setMiscReg(RegIndex misc_re [all...] |
/gem5/src/arch/null/ |
H A D | registers.hh | 50 const RegIndex ZeroReg = 0;
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/gem5/src/arch/arm/tracers/ |
H A D | tarmac_record.hh | 141 updateMisc(const TarmacContext& tarmCtx, RegIndex regRelIdx); 144 updateCC(const TarmacContext& tarmCtx, RegIndex regRelIdx); 147 updateFloat(const TarmacContext& tarmCtx, RegIndex regRelIdx); 150 updateInt(const TarmacContext& tarmCtx, RegIndex regRelIdx); 158 RegIndex regRel;
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H A D | tarmac_record_v8.hh | 106 RegIndex regRelIdx) override; 109 RegIndex regRelIdx) override;
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H A D | tarmac_record.cc | 191 RegIndex regRelIdx 218 RegIndex regRelIdx 231 RegIndex regRelIdx 244 RegIndex regRelIdx
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H A D | tarmac_base.hh | 107 RegIndex index;
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H A D | tarmac_record_v8.cc | 89 RegIndex regRelIdx 120 RegIndex regRelIdx
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/gem5/src/arch/sparc/ |
H A D | isa.hh | 162 RegIndex intRegMap[TotalInstIntRegs]; 214 RegIndex flatIndex = intRegMap[reg];
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