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/gem5/src/cpu/o3/ | ||
H A D | commit_impl.hh | 9948:6cbe5c9d0ebb Thu Oct 31 14:41:00 EDT 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: Fix O3 issuse with load+barrier instructions. Fix a problem in the O3 CPU for instructions that are both memory loads and memory barriers (e.g. load acquire) and to uncacheable memory. This combination can confuse the commit stage into commitng an instruction that hasn't executed and got it's value yet. At the same time refactor the code slightly to remove duplication between two of the cases. |
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