Searched hist:8822 (Results 1 - 7 of 7) sorted by relevance
/gem5/src/cpu/o3/ | ||
H A D | rob.hh | 8822:e7ae13867098 Fri Feb 10 09:37:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> O3 CPU: Provide the squashing instruction This patch adds a function to the ROB that will get the squashing instruction from the ROB's list of instructions. This squashing instruction is used for figuring out the macroop from which the fetch stage should fetch the microops. Further, a check has been added that if the instructions are to be fetched from the cache maintained by the fetch stage, then the data in the cache should be valid and the PC of the thread being fetched from is same as the address of the cache block. |
H A D | rob_impl.hh | 8822:e7ae13867098 Fri Feb 10 09:37:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> O3 CPU: Provide the squashing instruction This patch adds a function to the ROB that will get the squashing instruction from the ROB's list of instructions. This squashing instruction is used for figuring out the macroop from which the fetch stage should fetch the microops. Further, a check has been added that if the instructions are to be fetched from the cache maintained by the fetch stage, then the data in the cache should be valid and the PC of the thread being fetched from is same as the address of the cache block. |
H A D | commit_impl.hh | 8822:e7ae13867098 Fri Feb 10 09:37:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> O3 CPU: Provide the squashing instruction This patch adds a function to the ROB that will get the squashing instruction from the ROB's list of instructions. This squashing instruction is used for figuring out the macroop from which the fetch stage should fetch the microops. Further, a check has been added that if the instructions are to be fetched from the cache maintained by the fetch stage, then the data in the cache should be valid and the PC of the thread being fetched from is same as the address of the cache block. |
H A D | fetch_impl.hh | 8822:e7ae13867098 Fri Feb 10 09:37:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> O3 CPU: Provide the squashing instruction This patch adds a function to the ROB that will get the squashing instruction from the ROB's list of instructions. This squashing instruction is used for figuring out the macroop from which the fetch stage should fetch the microops. Further, a check has been added that if the instructions are to be fetched from the cache maintained by the fetch stage, then the data in the cache should be valid and the PC of the thread being fetched from is same as the address of the cache block. |
/gem5/src/arch/arm/ | ||
H A D | miscregs.cc | 12577:5cafe57f87e5 Wed Jan 24 12:39:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Adding IPA-Based Invalidating instructions This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L. Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | isa.hh | 12577:5cafe57f87e5 Wed Jan 24 12:39:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Adding IPA-Based Invalidating instructions This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L. Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | isa.cc | 12577:5cafe57f87e5 Wed Jan 24 12:39:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Adding IPA-Based Invalidating instructions This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L. Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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