Searched hist:7786 (Results 1 - 1 of 1) sorted by relevance

/gem5/src/cpu/o3/
H A Dlsq_unit.hh7786:bafa8a197088 Tue Dec 07 19:19:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).

The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.

Completed in 27 milliseconds