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/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dxchg.py7501:a75564db03c3 Wed Jul 21 12:55:00 EDT 2010 Tushar Krishna <Tushar.Krishna@amd.com> Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses
/gem5/src/arch/arm/isa/formats/
H A Ddata.isa7432:7501a6d33e3e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Combine some redundant cases in one of the data decode functions.

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