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/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/
H A Dadd_and_subtract.py6090:80d7669e9cdb Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of NEG.
6086:2ac9ab003d54 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of SUB.
6084:cb751de62299 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of SBB.
6083:c669a6f8fa9e Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of ADC.
6081:e5da3985fa99 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of ADD.
H A Dincrement_and_decrement.py6092:e4ffbb3546fa Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of DEC.
6091:d430acd6d5ce Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of INC.
/gem5/tests/
H A Dhalt.sh2934:0b091d7d00f0 Fri Jul 21 15:56:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.

configs/test/fs.py:
Pull out a lot of common code and put it into configs/common/FSConfig.py.
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dlogical.py6089:030c2a63fb61 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of NOT.
6087:7736bc8824a1 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of XOR.
6085:c210d3e04532 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of AND.
6082:5db340cc3c47 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of OR.
/gem5/src/systemc/
H A DTlm.py13873:9fd9b551f9d8 Mon Apr 15 22:56:00 EDT 2019 Gabe Black <gabeblack@google.com> systemc: Add Port types for initiator and target sockets.

These make it clear that a port represents a TLM socket, what direction
it faces, and what its width is.

Change-Id: Idcbea2b9b053f1e0685e011bc2c7de2468fb25b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18172
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/
H A Dbit_test.py6096:72f1239a1583 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of BTC.
6095:c36f932461d9 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of BTR.
6093:7b88298769c7 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of BTS.
/gem5/src/unittest/
H A Drefcnttest.cc7824:b36af60dcb91 Mon Jan 10 06:56:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> RefCount: Add a unit test for reference counting pointers.

This test exercises each of the functions in the reference counting pointer
implementation individually (except get()) and verifies they have some
minimially expected behavior. It also checks that reference counted objects
are freed when their usage count goes to 0 in some basic situations,
specifically a pointer being set to NULL and a pointer being deleted.
/gem5/ext/sst/
H A DLICENSE10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
H A DMakefile10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
H A DREADME10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
/gem5/src/mem/cache/prefetch/
H A Dslim_ampm.cc13700:56fa28e6fab4 Thu Jan 31 10:24:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Slim AMPM Prefetcher

Reference:
Towards Bandwidth-Efficient Prefetching with Slim AMPM.
Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.

Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already
in gem5).

Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Reviewed-on: https://gem5-review.googlesource.com/c/16383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dslim_ampm.hh13700:56fa28e6fab4 Thu Jan 31 10:24:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Slim AMPM Prefetcher

Reference:
Towards Bandwidth-Efficient Prefetching with Slim AMPM.
Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.

Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already
in gem5).

Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Reviewed-on: https://gem5-review.googlesource.com/c/16383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dassociative_set.hh13707:5aab50651a66 Thu Feb 21 15:56:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Add a mechanism to iterate all entries of an AssociativeSet

Added functions to obtain an iterator to access all entries of
an AssociativeSet container.

Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
Reviewed-on: https://gem5-review.googlesource.com/c/16582
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/dev/arm/
H A Ddisplay.cc14283:b02cde4661e1 Mon Aug 12 14:56:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add HDLcd DTB autogeneration

A Display has been defined. Its sole purpose is to generate the device
tree node to be referenced by the HDLcd device. The encoder parameters
are based on the existing node defined in:

system/arm/dt/armv8.dts

Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Ddisplay.hh14283:b02cde4661e1 Mon Aug 12 14:56:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add HDLcd DTB autogeneration

A Display has been defined. Its sole purpose is to generate the device
tree node to be referenced by the HDLcd device. The encoder parameters
are based on the existing node defined in:

system/arm/dt/armv8.dts

Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A DDisplay.py14283:b02cde4661e1 Mon Aug 12 14:56:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add HDLcd DTB autogeneration

A Display has been defined. Its sole purpose is to generate the device
tree node to be referenced by the HDLcd device. The encoder parameters
are based on the existing node defined in:

system/arm/dt/armv8.dts

Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Damba_fake.hh9806:3f262c18ad5d Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev/arm: get rid of AmbaDev namespace

It was confusing having an AmbaDev namespace along with an
AmbaDevice class. The namespace stuff is now moved in to
a new base AmbaDevice class, which is a mixin for classes
AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice
to provide the readId function as an inherited member function.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
/gem5/src/sim/
H A DDVFSHandler.py10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
/gem5/src/arch/x86/
H A Dcpuid.hh9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
/gem5/src/arch/null/
H A Dcpu_dummy.hh10102:b5de69974a2e Fri Mar 07 15:56:00 EST 2014 Ali Saidi <ali.saidi@arm.com> mem: Wakeup sleeping CPUs without caches on LLSC

For systems without caches, the LLSC code does not get snoops for
wake-ups. We add the LLSC code in the abstract memory to do the job
for us.
/gem5/src/mem/cache/replacement_policies/
H A Dsecond_chance_rp.cc12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dsecond_chance_rp.hh12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/mem/cache/
H A Dwrite_queue.hh12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/tests/test-progs/hello/src/
H A Dhello.c12881:57339a66cd77 Thu Sep 21 20:56:00 EDT 2017 Jason Lowe-Power <jason@lowepower.com> tests: Fix hello.c test program

Update the hello test to have a sane return code.

Change-Id: I9576b71ee995d8aa410c4ed19d44cc4e9fad10ee
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/4881
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dxchg.py6088:c698cbf56cf1 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of XCHG.

Completed in 45 milliseconds

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