Searched hist:13395 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/systemc/core/ | ||
| H A D | sc_port.cc | 13332:03eec201e55a Wed Oct 10 22:03:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Warn about using deprecated sc_port constructors. This gets rid of one of the last instances of a warning about unimplemented functionality. Change-Id: I3d8e50ea45554cba969118ce873ed3d2b041ec43 Reviewed-on: https://gem5-review.googlesource.com/c/13395 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/systemc/ext/core/ | ||
| H A D | sc_port.hh | 13332:03eec201e55a Wed Oct 10 22:03:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Warn about using deprecated sc_port constructors. This gets rid of one of the last instances of a warning about unimplemented functionality. Change-Id: I3d8e50ea45554cba969118ce873ed3d2b041ec43 Reviewed-on: https://gem5-review.googlesource.com/c/13395 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/arm/ | ||
| H A D | miscregs.cc | 13395:0f064dae9f6b Wed Oct 31 12:45:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Implement AArch32 RVBAR RVBAR has been added to the system register list since ARMv8.0-A. It is implemented only if the highest Exception Level is different (minor) than EL3. If that's not the case, MVBAR is used. Since the two registers are mutually exclusive (depending on the presence of EL3), they share the same coprocessor numbers: p15, 0, c12, c0, 1 Rather than introducing a new register alias, we overload MVBAR so that it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR). N.B MVBAR is RW, whereas RVBAR is RO Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13999 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | isa.hh | 13395:0f064dae9f6b Wed Oct 31 12:45:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Implement AArch32 RVBAR RVBAR has been added to the system register list since ARMv8.0-A. It is implemented only if the highest Exception Level is different (minor) than EL3. If that's not the case, MVBAR is used. Since the two registers are mutually exclusive (depending on the presence of EL3), they share the same coprocessor numbers: p15, 0, c12, c0, 1 Rather than introducing a new register alias, we overload MVBAR so that it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR). N.B MVBAR is RW, whereas RVBAR is RO Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13999 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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