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/gem5/src/cpu/
H A Dbase.cc11221:2fb745f69681 Fri Nov 20 15:50:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Enforce 1 interrupt controller per thread

Consider it a fatal configuration error if the number of interrupt
controllers doesn't match the number of threads in an SMT
configuration.

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