Searched refs:vrf (Results 1 - 9 of 9) sorted by relevance
/gem5/src/gpu-compute/ |
H A D | wavefront.cc | 299 return physicalVgprIndex % computeUnit->vrf[simdId]->numRegs(); 405 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 410 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 445 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 449 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 482 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 486 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 521 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii, 526 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) { 547 computeUnit->vrf[simdI [all...] |
H A D | local_memory_pipeline.cc | 71 w->computeUnit->vrf[w->simdId]->
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H A D | schedule_stage.cc | 101 if (computeUnit->vrf[simdId]->
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H A D | global_memory_pipeline.cc | 77 w->computeUnit->vrf[w->simdId]->
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H A D | compute_unit.cc | 64 cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs), 155 for (int i = 0; i < vrf.size(); ++i) { 156 vrf[i]->setParent(this); 159 numVecRegsPerSimd = vrf[0]->numRegs(); 209 vrf[regInfo.first]->markReg(regInfo.second, sizeof(uint32_t), 222 vrf[i]->updateEvents(); 352 w->startVgprIndex = vrf[m % numSIMDs]->manager-> 416 vregAvail = vrf[j]->manager->canAllocate(numWfsPerSimd[j],
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H A D | compute_unit.hh | 140 std::vector<VectorRegisterFile*> vrf; member in class:ComputeUnit
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/gem5/src/arch/hsail/insts/ |
H A D | main.cc | 169 w->computeUnit->vrf[w->simdId]->numRegs(); 171 w->computeUnit->vrf[w->simdId]->manager->
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H A D | mem.hh | 556 w->computeUnit->vrf[w->simdId]->write<c0>(physVgpr, 567 vrf[w->simdId]->exec(gpuDynInst->seqNum(), w, regVec, 1536 w->computeUnit->vrf[w->simdId]->write<CType>(physVgpr, *p1, i); 1545 vrf[w->simdId]->exec(gpuDynInst->seqNum(), w, regVec,
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/gem5/src/arch/hsail/ |
H A D | operand.hh | 167 ret = (w->computeUnit->vrf[w->simdId]-> 172 ret = (w->computeUnit->vrf[w->simdId]-> 177 ret = w->computeUnit->vrf[w->simdId]-> 210 w->computeUnit->vrf[w->simdId]->write<OperandType>(vgprIdx,val,lane); 222 w->computeUnit->vrf[w->simdId]->write<uint32_t>(vgprIdx, val, lane); 268 return w->computeUnit->vrf[w->simdId]->read<OperandType>(vgprIdx,lane); 283 w->computeUnit->vrf[w->simdId]->write<OperandType>(vgprIdx,val,lane);
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