Searched refs:vrf (Results 1 - 9 of 9) sorted by relevance

/gem5/src/gpu-compute/
H A Dwavefront.cc299 return physicalVgprIndex % computeUnit->vrf[simdId]->numRegs();
405 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
410 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) {
445 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
449 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) {
482 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
486 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) {
521 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
526 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) {
547 computeUnit->vrf[simdI
[all...]
H A Dlocal_memory_pipeline.cc71 w->computeUnit->vrf[w->simdId]->
H A Dschedule_stage.cc101 if (computeUnit->vrf[simdId]->
H A Dglobal_memory_pipeline.cc77 w->computeUnit->vrf[w->simdId]->
H A Dcompute_unit.cc64 cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs),
155 for (int i = 0; i < vrf.size(); ++i) {
156 vrf[i]->setParent(this);
159 numVecRegsPerSimd = vrf[0]->numRegs();
209 vrf[regInfo.first]->markReg(regInfo.second, sizeof(uint32_t),
222 vrf[i]->updateEvents();
352 w->startVgprIndex = vrf[m % numSIMDs]->manager->
416 vregAvail = vrf[j]->manager->canAllocate(numWfsPerSimd[j],
H A Dcompute_unit.hh140 std::vector<VectorRegisterFile*> vrf; member in class:ComputeUnit
/gem5/src/arch/hsail/insts/
H A Dmain.cc169 w->computeUnit->vrf[w->simdId]->numRegs();
171 w->computeUnit->vrf[w->simdId]->manager->
H A Dmem.hh556 w->computeUnit->vrf[w->simdId]->write<c0>(physVgpr,
567 vrf[w->simdId]->exec(gpuDynInst->seqNum(), w, regVec,
1536 w->computeUnit->vrf[w->simdId]->write<CType>(physVgpr, *p1, i);
1545 vrf[w->simdId]->exec(gpuDynInst->seqNum(), w, regVec,
/gem5/src/arch/hsail/
H A Doperand.hh167 ret = (w->computeUnit->vrf[w->simdId]->
172 ret = (w->computeUnit->vrf[w->simdId]->
177 ret = w->computeUnit->vrf[w->simdId]->
210 w->computeUnit->vrf[w->simdId]->write<OperandType>(vgprIdx,val,lane);
222 w->computeUnit->vrf[w->simdId]->write<uint32_t>(vgprIdx, val, lane);
268 return w->computeUnit->vrf[w->simdId]->read<OperandType>(vgprIdx,lane);
283 w->computeUnit->vrf[w->simdId]->write<OperandType>(vgprIdx,val,lane);

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