Searched refs:tcStatus (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/mips/
H A Dmt.hh200 TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS); local
213 tidTCStatus.asid = tcStatus.asid;
271 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); local
272 tcStatus.a = 0;
273 tc->setMiscReg(MISCREG_TC_STATUS, tcStatus);
286 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); local
290 if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) {
309 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); local
312 status.cu = tcStatus.tcu;
313 status.mx = tcStatus
327 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); local
[all...]
H A Disa.cc371 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS); local
372 tcStatus.a = 1;
373 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
377 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
378 tcStatus.da = 1;
379 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
544 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); local
548 if (tcHalt.h == 1 || tcStatus.a == 0) {
550 } else if (tcHalt.h == 0 && tcStatus.a == 1) {

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