Searched refs:stores (Results 1 - 3 of 3) sorted by relevance

/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh148 loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
180 loads = stores = storesToWB = 0;
210 .desc("Number of loads that had data forwarded from stores");
230 .desc("Number of stores squashed");
320 assert(stores < storeQueue.capacity());
332 ++stores;
363 DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n",
364 1 + storeQueue.capacity(), stores);
365 return storeQueue.capacity() - stores;
604 assert(stores !
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H A Dlsq_unit.hh279 /** Commits stores older than a specific sequence number. */
282 /** Writes back stores. */
309 /** Returns the number of stores in the SQ. */
310 int numStores() { return stores; }
328 bool sqEmpty() const { return stores == 0; }
331 unsigned getCount() { return loads + stores; }
333 /** Returns if there are any stores to writeback. */
336 /** Returns the number of stores to writeback. */
436 /** Writeback event, specifically for when stores forward data to loads. */
492 int stores; member in class:LSQUnit
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Ddirty.S24 # Set up MPRV with MPP=S, so loads and stores use S-mode

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