Searched refs:stage2Mmu (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/arch/arm/ |
| H A D | tlb.hh | 165 Stage2MMU *stage2Mmu; member in class:ArmISA::TLB
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| H A D | tlb.cc | 80 stage2Mmu(NULL), test(nullptr), rangeMRU(1),
106 if (stage2Mmu && !isStage2)
107 stage2Tlb = stage2Mmu->stage2Tlb();
113 stage2Mmu = m;
1289 return &stage2Mmu->getDMAPort();
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| H A D | table_walker.cc | 61 stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId),
104 stage2Mmu = m;
112 fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n");
1994 Stage2MMU::Stage2Translation(*stage2Mmu, data, event,
1997 stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes,
2001 fault = stage2Mmu->readDataUntimed(currState->tc,
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| H A D | table_walker.hh | 827 Stage2MMU *stage2Mmu; member in class:ArmISA::TableWalker::LongDescriptor
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