Searched refs:rev (Results 1 - 9 of 9) sorted by relevance
/gem5/util/ |
H A D | hgfilesize.py | 21 existing_tip = context.changectx(repo, node).rev() 22 new_tip = context.changectx(repo, 'tip').rev() 23 for rev in xrange(existing_tip, new_tip + 1): 24 ctx = context.changectx(repo, rev)
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/gem5/util/maint/ |
H A D | list_changes.py | 48 def __init__(self, rev): 49 self.rev = rev 64 ["show", "--format=%B", "--no-patch", str(self.rev) ] 106 return "%s: %s" % (self.rev[0:8], self.log[0]) 123 [ "git", "rev-list", query, '--'] + paths 129 for rev in changes.rstrip("\n").split("\n"): 130 assert rev != "" 131 yield Commit(rev) 188 for rev i [all...] |
H A D | create_patches.sh | 76 git rev-parse --verify -q "$1" > /dev/null 124 SHA_PATCHES=`git rev-parse "$BRANCH"` 126 SHA_UPSTREAM=`git rev-parse "$UPSTREAM"`
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/gem5/ext/pybind11/tests/ |
H A D | test_sequences_and_iterators.py | 63 rev = reversed(s) 76 assert allclose(rev, expected) 78 assert rev == rev2 80 rev[0::2] = m.Sequence([2.0, 2.0, 2.0]) 83 assert allclose(rev, [2, 56.78, 2, 0, 2]) 90 del rev
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/gem5/ext/ |
H A D | git-commit-msg | 176 if parent=`git rev-parse "HEAD^0" 2>/dev/null`
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/gem5/src/arch/arm/linux/ |
H A D | atag.hh | 124 void rev(uint32_t i) { storage[2] = i; } function in class:AtagRev 245 u32 rev;
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/gem5/src/arch/mips/ |
H A D | pra_constants.hh | 206 Bitfield<7, 0> rev; member in namespace:MipsISA
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H A D | isa.cc | 184 procId.rev = cp.CP0_PRId_Revision;
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/gem5/src/arch/riscv/ |
H A D | pra_constants.hh | 206 Bitfield<7, 0> rev; member in namespace:RiscvISA
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