Searched refs:retries (Results 1 - 6 of 6) sorted by relevance

/gem5/src/gpu-compute/
H A Dfetch_unit.cc169 assert(computeUnit->sqcTLBPort->retries.size() > 0);
174 computeUnit->sqcTLBPort->retries.push_back(pkt);
185 computeUnit->sqcTLBPort->retries.push_back(pkt);
238 computeUnit->sqcPort->retries.push_back(std::make_pair(pkt,
H A Dcompute_unit.cc687 int len = retries.size();
692 PacketPtr pkt = retries.front().first;
693 GPUDynInstPtr gpuDynInst M5_VAR_USED = retries.front().second;
700 * pass and the data port should expect multiple retries. */
706 retries.pop_front();
722 int len = retries.size();
727 PacketPtr pkt = retries.front().first;
728 Wavefront *wavefront M5_VAR_USED = retries.front().second;
737 retries.pop_front();
857 assert(tlbPort[tlbPort_index]->retries
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H A Dtlb_coalescer.hh190 std::deque<PacketPtr> retries; member in class:TLBCoalescer::MemSidePort
H A Dcompute_unit.hh450 std::deque<std::pair<PacketPtr, GPUDynInstPtr>> retries; member in class:ComputeUnit::DataPort
491 std::deque<std::pair<PacketPtr, Wavefront*>> retries; member in class:ComputeUnit::SQCPort
528 std::deque<PacketPtr> retries; member in class:ComputeUnit::DTLBPort
575 std::deque<PacketPtr> retries; member in class:ComputeUnit::ITLBPort
618 std::queue<PacketPtr> retries; member in class:ComputeUnit::LDSPort
H A Dgpu_tlb.hh293 std::deque<PacketPtr> retries; member in class:X86ISA::GpuTLB::MemSidePort
H A Dgpu_tlb.cc1293 memSidePort[0]->retries.push_back(pkt);
1595 // The CPUSidePort never sends anything but replies. No retries
1636 // No retries should reach the TLB. The retries

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