Searched refs:lr (Results 1 - 9 of 9) sorted by relevance

/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ua/
H A Dtest.S18 lr.w t2, 0(a0)
H A Dlrsc.S39 lr.w a1, (a1); \
49 1: lr.w a4, (a0)
/gem5/util/m5/
H A Dm5op_arm.S64 mov pc,lr
/gem5/src/arch/power/
H A Dremote_gdb.hh63 uint32_t lr; member in struct:PowerISA::RemoteGDB::PowerGdbRegCache::__anon5
H A Dremote_gdb.cc192 r.lr = htobe((uint32_t)context->readIntReg(INTREG_LR));
211 context->setIntReg(INTREG_LR, betoh(r.lr));
/gem5/src/dev/arm/
H A Dvgic.cc116 ListReg *lr = &vid->LR[i]; local
118 pkt->setLE<uint32_t>(lr->VirtualID |
119 (((int)lr->CpuID) << 10));
122 if (lr->HW)
124 *lr);
125 lr->State = LR_ACTIVE;
127 lr->VirtualID, lr->CpuID, i, lr->EOI);
268 ListReg *lr
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/gem5/util/statetrace/arch/arm/
H A Dtracechild.cc243 uint32_t lr = getRegVal(14); local
257 // <possible MOV lr,...>
270 lrOp = ptrace(PTRACE_PEEKDATA, pid, lr, 0);
271 ptrace(PTRACE_POKEDATA, pid, lr, bkpt_inst);
277 ptrace(PTRACE_POKEDATA, pid, lr, lrOp);
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64uamt/
H A Dlrsc_d.S39 // This code tests lr.d and sc.d instructions in multi-threading system.
82 lr.d.aq s2, (a0) // load and reserve a0
83 bnez s2, 1b // retry lr if the lock is being held
/gem5/ext/ply/ply/
H A Dyacc.py3069 lr = LRTable()
3071 read_signature = lr.read_pickle(picklefile)
3073 read_signature = lr.read_table(tabmodule)
3076 lr.bind_callables(pinfo.pdict)
3077 parser = LRParser(lr,pinfo.error_func)
3220 lr = LRGeneratedTable(grammar,method,debuglog)
3223 num_sr = len(lr.sr_conflicts)
3231 num_rr = len(lr.rr_conflicts)
3238 if debug and (lr.sr_conflicts or lr
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