Searched refs:lineWidth (Results 1 - 5 of 5) sorted by relevance

/gem5/src/cpu/minor/
H A Dpipe_data.hh189 unsigned int lineWidth; member in class:Minor::ForwardLineData
200 * only valid upto lineWidth - 1. */
210 lineWidth(0),
H A Dpipe_data.cc175 lineWidth = width_;
188 lineWidth = packet->req->getSize();
H A Dfetch2.cc306 * using more than one input line. Note that lineWidth will be 0
310 fetch_info.inputIndex < line_in->lineWidth) && /* More input */
335 " lineBaseAddr: 0x%x lineWidth: 0x%x\n",
337 line_in->lineWidth);
433 " lineWidth: %d output_index: %d inputIndex: %d"
436 line_in->lineWidth, output_index, fetch_info.inputIndex,
474 " inputIndex: 0x%x lineBaseAddr: 0x%x lineWidth: 0x%x\n",
476 line_in->lineWidth);
521 } else if (fetch_info.inputIndex == line_in->lineWidth) {
H A Dlsq.cc416 unsigned int line_width = port.lineWidth;
431 * The first transfer (0) can be up to lineWidth in size.
432 * All the middle transfers (1-3) are lineWidth in size
433 * The last transfer (4) can be from zero to lineWidth - 1 in size
1406 lineWidth((line_width == 0 ? cpu.cacheLineSize() : line_width)),
1443 if ((lineWidth & (lineWidth - 1)) != 0) {
1444 fatal("%s: lineWidth: %d must be a power of 2\n", name(), lineWidth);
1585 bool needs_burst = transferNeedsBurst(addr, size, lineWidth);
[all...]
H A Dlsq.hh545 const unsigned int lineWidth; member in class:Minor::LSQ

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