Searched refs:fsw (Results 1 - 5 of 5) sorted by relevance

/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64uf/
H A Dldst.S7 # This test verifies that flw, fld, fsw, and fsd work properly.
16 TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1))
17 TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1))
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ud/
H A Dldst.S7 # This test verifies that flw, fld, fsw, and fsd work properly.
18 TEST_CASE(3, a0, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0))
19 TEST_CASE(4, a0, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0))
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc74 uint16_t fsw; member in struct:FXSave
262 const unsigned top((fpu.fsw >> 11) & 0x7);
267 fpu.fsw, top,
269 (fpu.fsw & CC0Bit) ? "C0" : "",
270 (fpu.fsw & CC1Bit) ? "C1" : "",
271 (fpu.fsw & CC2Bit) ? "C2" : "",
272 (fpu.fsw & CC3Bit) ? "C3" : "",
274 (fpu.fsw & IEBit) ? "I" : "",
275 (fpu.fsw & DEBit) ? "D" : "",
276 (fpu.fsw
[all...]
/gem5/src/arch/x86/
H A Disa.cc146 RegVal fsw = regVal[MISCREG_FSW]; local
148 return insertBits(fsw, 13, 11, top);
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h1160 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)

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