Searched refs:endian (Results 1 - 9 of 9) sorted by relevance
| /gem5/src/mem/ |
| H A D | packet_access.hh | 87 Packet::get(ByteOrder endian) const
89 switch (endian) {
126 Packet::set(T v, ByteOrder endian) argument
128 switch (endian) {
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| H A D | packet.cc | 340 Packet::getUintX(ByteOrder endian) const
344 return (uint64_t)get<uint8_t>(endian);
346 return (uint64_t)get<uint16_t>(endian);
348 return (uint64_t)get<uint32_t>(endian);
350 return (uint64_t)get<uint64_t>(endian);
357 Packet::setUintX(uint64_t w, ByteOrder endian) argument
361 set<uint8_t>((uint8_t)w, endian);
364 set<uint16_t>((uint16_t)w, endian);
367 set<uint32_t>((uint32_t)w, endian);
370 set<uint64_t>((uint64_t)w, endian);
[all...] |
| H A D | packet.hh | 1108 * Get the data in the packet byte swapped from big endian to
1109 * host endian.
1115 * Get the data in the packet byte swapped from little endian to
1116 * host endian.
1126 T get(ByteOrder endian) const;
1131 * endian.
1138 /** Set the value in the data pointer to v as big endian. */
1142 /** Set the value in the data pointer to v as little endian. */
1151 void set(T v, ByteOrder endian);
1154 /** Set the value in the data pointer to v as guest endian
[all...] |
| /gem5/src/systemc/ext/utils/ |
| H A D | endian.hh | 24 * Modified by Caleb Epstein to use <endian.h> with GNU libc and to
31 // GNU libc offers the helpful header <endian.h> which defines
35 # include <endian.h>
76 # error The file boost/detail/endian.hpp needs to be set up for your CPU type.
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| /gem5/src/arch/arm/ |
| H A D | semihosting.cc | 174 ByteOrder endian = ArmISA::byteOrder(tc); local
179 argv[i + 1] = proxy.read<uint64_t>(param + i * 8, endian);
209 ByteOrder endian = ArmISA::byteOrder(tc); local
214 argv[i + 1] = proxy.read<uint32_t>(param + i * 4, endian);
552 ByteOrder endian = ArmISA::byteOrder(tc); local
556 proxy.write<uint64_t>(argv[0] + 1 * 8, cmdLine.size(), endian);
558 proxy.write<uint32_t>(argv[0] + 1 * 4, cmdLine.size(), endian);
607 ByteOrder endian = ArmISA::byteOrder(tc); local
609 proxy.write<uint64_t>(base + 0 * 8, heap_base, endian);
610 proxy.write<uint64_t>(base + 1 * 8, heap_limit, endian);
662 ByteOrder endian = ArmISA::byteOrder(tc); local
[all...] |
| /gem5/src/mem/cache/prefetch/ |
| H A D | base.hh | 205 get(ByteOrder endian) const
210 switch (endian) {
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| /gem5/configs/common/ |
| H A D | cpu2000.py | 670 self.endian = 'lendian'
672 self.endian = 'bendian'
679 self.args = [ '%s.raw' % self.endian ]
683 self.args = [ '%s.raw' % self.endian ]
687 self.args = [ '%s.raw' % self.endian ]
691 self.args = [ '%s.raw' % self.endian ]
695 self.args = [ '%s.raw' % self.endian ]
700 self.args = [ '%s1.raw' % self.endian ]
708 self.args = [ '%s2.raw' % self.endian ]
714 self.args = [ '%s3.raw' % self.endian ]
[all...] |
| /gem5/src/dev/storage/ |
| H A D | ide_atareg.h | 37 #include <endian.h>
43 #include <machine/endian.h>
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| /gem5/src/sim/ |
| H A D | byteswap.hh | 44 #include <endian.h>
52 #include <machine/endian.h>
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