Searched refs:enableDebug (Results 1 - 2 of 2) sorted by relevance

/gem5/src/mem/
H A DDRAMSim2.py56 enableDebug = Param.Bool(False, "Enable DRAMSim2 debug output") variable in class:DRAMSim2
H A Ddramsim2.cc53 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),

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