Searched refs:back (Results 1 - 25 of 67) sorted by relevance

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/gem5/src/systemc/ext/tlm_core/2/generic_payload/
H A Darray.hh79 if ((*this)[m_entries.back()]) {
81 (*this)[m_entries.back()]->free();
84 (*this)[m_entries.back()] = nullptr;
/gem5/util/tlm/src/
H A Dsc_mm.cc66 gp* result = freePayloads.back();
/gem5/src/systemc/tlm_bridge/
H A Dsc_mm.cc59 gp *result = freePayloads.back();
/gem5/ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/
H A Dtlm_array.h104 if ((*this)[m_entries.back()]) //we make sure no one cleared the slot manually
105 (*this)[m_entries.back()]->free();//...and then we call free on the content of the slot
106 (*this)[m_entries.back()]=0; //afterwards we set the slot to NULL
/gem5/ext/mcpat/cacti/
H A Dnuca.cc253 nuca_list.back()->nuca_pda.cycle_time = router_s[ro]->cycle_time;
267 1 /(nuca_list.back()->nuca_pda.cycle_time *
271 1 / (nuca_list.back()->nuca_pda.cycle_time *
319 (nuca_list.back()->nuca_pda.cycle_time *
354 nuca_list.back()->wire_pda.power.readOp.dynamic =
358 nuca_list.back()->avg_hops = opt_avg_hop;
360 nuca_list.back()->h_wire = wire_horizontal[wr];
361 nuca_list.back()->v_wire = wire_vertical[wr];
362 nuca_list.back()->router = router_s[ro];
365 nuca_list.back()
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H A DUcache.cc163 tag_arr.back(), 0, NULL, NULL,
171 data_arr.back(), 0, NULL, NULL,
177 tag_arr.back()->wt = (enum Wire_type) wr;
178 tag_res->update_min_values(tag_arr.back());
182 data_arr.back()->wt = (enum Wire_type) wr;
183 data_res->update_min_values(data_arr.back());
205 delete data_arr.back();
206 delete tag_arr.back();
620 bool v = check_mem_org(*list.back(), min);
622 cur_cost = wt_delay * (list.back()
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/gem5/ext/pybind11/tests/
H A Dtest_stl.cpp102 v.back()[0].emplace_back(); // add a map to the array
103 v.back()[0].back().emplace("b", RValueCaster{});
104 v.back()[0].back().emplace("c", RValueCaster{});
105 v.back()[1].emplace_back(); // add a map to the array
106 v.back()[1].back().emplace("a", RValueCaster{});
113 lvn["a"].back().emplace_back(); // add an array
115 lvn["a"].back()
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H A Dtest_opaque_types.cpp30 .def("back", (std::string &(StringList::*)()) &StringList::back)
H A Dtest_opaque_types.py11 assert lst.back() == "Element 2"
/gem5/src/gpu-compute/
H A Dkernel_cfg.cc118 basicBlocks.back()->size = block_size;
125 basicBlocks.back()->size = block_size;
133 BasicBlock* exit_bb = basicBlocks.back().get();
173 basicBlocks.back()->postDominatorIds.insert(basicBlocks.back()->id);
H A Dcl_driver.cc64 kernels.back()->setReadonlyData((uint8_t*)obj->readonlyData);
65 int kern_funcargs_size = kernels.back()->funcarg_size;
195 kernels.back()->getSize(HsaCode::MemorySegment::READONLY);
199 kernels.back()->readonly_data,
H A Dtlb_coalescer.cc132 coalesced_state->reqCnt.back() += incoming_state->reqCnt.back();
172 // we are sending the packet back, so pop the reqCnt associated
204 SlavePort *return_port = sender_state->ports.back();
208 // send the translation back
242 // push back the port to remember the path back
256 req_cnt = sender_state->reqCnt.back();
262 req_cnt = sender_state->reqCnt.back();
471 int req_cnt = tmp_sender_state->reqCnt.back();
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/gem5/ext/systemc/src/sysc/utils/
H A Dsc_list.h62 void* back() const;
130 T back() const { return (T)sc_plist_base::back(); } function in class:sc_core::sc_plist
/gem5/src/systemc/core/
H A Devent.hh118 t = senses.back();
136 t = senses.back();
H A Dmodule.cc97 if (_modules.empty() || _modules.back() != this)
196 return _modules.back();
H A Dsc_attr.cc105 std::swap(attr, cltn.back());
H A Devent.cc103 std::swap(*it, topLevelEvents.back());
108 std::swap(*it, allEvents.back());
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_attribute.cpp143 std::swap( m_cltn[i], m_cltn.back() );
/gem5/src/cpu/pred/
H A Dbpred_unit.cc351 predHist[tid].back().seqNum <= done_sn) {
353 update(tid, predHist[tid].back().pc,
354 predHist[tid].back().predTaken,
355 predHist[tid].back().bpHistory, false,
356 predHist[tid].back().inst,
357 predHist[tid].back().target);
360 iPred->commit(done_sn, tid, predHist[tid].back().indirectHistory);
/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh139 // atomics), so it can complete without writing back
306 assert(!loadQueue.back().valid());
307 loadQueue.back().set(load_inst);
330 storeQueue.back().set(store_inst);
459 * all instructions that will execute before the store writes back. Thus,
688 // been marked as able to write back.
693 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
721 DPRINTF(LSQUnit, "Writing back blocked store\n");
733 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
738 // Store didn't write any data so no need to write it back t
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/gem5/src/base/
H A Dlogging.hh100 if (str.length() && str.back() != '\n' && str.back() != '\r')
H A Dcircular_queue.test.cc67 * of front() and back() (head an tail). Since we are just
69 * value to be fixed and the back value to change, matching
79 ASSERT_EQ(cq.back(), first_element);
84 ASSERT_EQ(cq.back(), second_element);
170 * values of (front() and back())
184 ASSERT_EQ(*(cq.end() - 1), cq.back());
H A Dcp_annotate.cc195 int prev_smi = smStack[sid].back();
276 int smib = smStack[sid].back();
293 "State machine ending:%s sysi:%d id:%#x back:%d getSm:%d\n",
294 sm, sysi, smMap[smib-1].second.second, smStack[sid].back(),
297 smStack[sid].back());
299 int smi = smStack[sid].back();
303 DPRINTF(Annotate, "Linking %d back to %d\n", smi, lnMap[smi]);
383 int smi = smStack[sid].back();
412 // return back to symbol table based states
414 int smi = smStack[sid].back();
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/gem5/src/mem/ruby/structures/
H A DWireBuffer.cc121 m_message_queue.back() = node;
/gem5/src/dev/arm/
H A Dflash_device.cc262 planeEventQueue[count].back().time;
269 schedule(planeEvent, planeEventQueue[count].back().time);
270 else if (planeEventQueue[count].back().time < planeEvent.when())
272 planeEventQueue[plane_address].back().time, true);
279 planeEventQueue[plane_address].back().function = event;

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