/gem5/src/systemc/ext/tlm_core/2/generic_payload/ |
H A D | array.hh | 79 if ((*this)[m_entries.back()]) { 81 (*this)[m_entries.back()]->free(); 84 (*this)[m_entries.back()] = nullptr;
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/gem5/util/tlm/src/ |
H A D | sc_mm.cc | 66 gp* result = freePayloads.back();
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/gem5/src/systemc/tlm_bridge/ |
H A D | sc_mm.cc | 59 gp *result = freePayloads.back();
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/gem5/ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/ |
H A D | tlm_array.h | 104 if ((*this)[m_entries.back()]) //we make sure no one cleared the slot manually 105 (*this)[m_entries.back()]->free();//...and then we call free on the content of the slot 106 (*this)[m_entries.back()]=0; //afterwards we set the slot to NULL
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/gem5/ext/mcpat/cacti/ |
H A D | nuca.cc | 253 nuca_list.back()->nuca_pda.cycle_time = router_s[ro]->cycle_time; 267 1 /(nuca_list.back()->nuca_pda.cycle_time * 271 1 / (nuca_list.back()->nuca_pda.cycle_time * 319 (nuca_list.back()->nuca_pda.cycle_time * 354 nuca_list.back()->wire_pda.power.readOp.dynamic = 358 nuca_list.back()->avg_hops = opt_avg_hop; 360 nuca_list.back()->h_wire = wire_horizontal[wr]; 361 nuca_list.back()->v_wire = wire_vertical[wr]; 362 nuca_list.back()->router = router_s[ro]; 365 nuca_list.back() [all...] |
H A D | Ucache.cc | 163 tag_arr.back(), 0, NULL, NULL, 171 data_arr.back(), 0, NULL, NULL, 177 tag_arr.back()->wt = (enum Wire_type) wr; 178 tag_res->update_min_values(tag_arr.back()); 182 data_arr.back()->wt = (enum Wire_type) wr; 183 data_res->update_min_values(data_arr.back()); 205 delete data_arr.back(); 206 delete tag_arr.back(); 620 bool v = check_mem_org(*list.back(), min); 622 cur_cost = wt_delay * (list.back() [all...] |
/gem5/ext/pybind11/tests/ |
H A D | test_stl.cpp | 102 v.back()[0].emplace_back(); // add a map to the array 103 v.back()[0].back().emplace("b", RValueCaster{}); 104 v.back()[0].back().emplace("c", RValueCaster{}); 105 v.back()[1].emplace_back(); // add a map to the array 106 v.back()[1].back().emplace("a", RValueCaster{}); 113 lvn["a"].back().emplace_back(); // add an array 115 lvn["a"].back() [all...] |
H A D | test_opaque_types.cpp | 30 .def("back", (std::string &(StringList::*)()) &StringList::back)
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H A D | test_opaque_types.py | 11 assert lst.back() == "Element 2"
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/gem5/src/gpu-compute/ |
H A D | kernel_cfg.cc | 118 basicBlocks.back()->size = block_size; 125 basicBlocks.back()->size = block_size; 133 BasicBlock* exit_bb = basicBlocks.back().get(); 173 basicBlocks.back()->postDominatorIds.insert(basicBlocks.back()->id);
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H A D | cl_driver.cc | 64 kernels.back()->setReadonlyData((uint8_t*)obj->readonlyData); 65 int kern_funcargs_size = kernels.back()->funcarg_size; 195 kernels.back()->getSize(HsaCode::MemorySegment::READONLY); 199 kernels.back()->readonly_data,
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H A D | tlb_coalescer.cc | 132 coalesced_state->reqCnt.back() += incoming_state->reqCnt.back(); 172 // we are sending the packet back, so pop the reqCnt associated 204 SlavePort *return_port = sender_state->ports.back(); 208 // send the translation back 242 // push back the port to remember the path back 256 req_cnt = sender_state->reqCnt.back(); 262 req_cnt = sender_state->reqCnt.back(); 471 int req_cnt = tmp_sender_state->reqCnt.back(); [all...] |
/gem5/ext/systemc/src/sysc/utils/ |
H A D | sc_list.h | 62 void* back() const; 130 T back() const { return (T)sc_plist_base::back(); } function in class:sc_core::sc_plist
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/gem5/src/systemc/core/ |
H A D | event.hh | 118 t = senses.back(); 136 t = senses.back();
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H A D | module.cc | 97 if (_modules.empty() || _modules.back() != this) 196 return _modules.back();
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H A D | sc_attr.cc | 105 std::swap(attr, cltn.back());
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H A D | event.cc | 103 std::swap(*it, topLevelEvents.back()); 108 std::swap(*it, allEvents.back());
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/gem5/ext/systemc/src/sysc/kernel/ |
H A D | sc_attribute.cpp | 143 std::swap( m_cltn[i], m_cltn.back() );
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/gem5/src/cpu/pred/ |
H A D | bpred_unit.cc | 351 predHist[tid].back().seqNum <= done_sn) { 353 update(tid, predHist[tid].back().pc, 354 predHist[tid].back().predTaken, 355 predHist[tid].back().bpHistory, false, 356 predHist[tid].back().inst, 357 predHist[tid].back().target); 360 iPred->commit(done_sn, tid, predHist[tid].back().indirectHistory);
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/gem5/src/cpu/o3/ |
H A D | lsq_unit_impl.hh | 139 // atomics), so it can complete without writing back 306 assert(!loadQueue.back().valid()); 307 loadQueue.back().set(load_inst); 330 storeQueue.back().set(store_inst); 459 * all instructions that will execute before the store writes back. Thus, 688 // been marked as able to write back. 693 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 721 DPRINTF(LSQUnit, "Writing back blocked store\n"); 733 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 738 // Store didn't write any data so no need to write it back t [all...] |
/gem5/src/base/ |
H A D | logging.hh | 100 if (str.length() && str.back() != '\n' && str.back() != '\r')
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H A D | circular_queue.test.cc | 67 * of front() and back() (head an tail). Since we are just 69 * value to be fixed and the back value to change, matching 79 ASSERT_EQ(cq.back(), first_element); 84 ASSERT_EQ(cq.back(), second_element); 170 * values of (front() and back()) 184 ASSERT_EQ(*(cq.end() - 1), cq.back());
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H A D | cp_annotate.cc | 195 int prev_smi = smStack[sid].back(); 276 int smib = smStack[sid].back(); 293 "State machine ending:%s sysi:%d id:%#x back:%d getSm:%d\n", 294 sm, sysi, smMap[smib-1].second.second, smStack[sid].back(), 297 smStack[sid].back()); 299 int smi = smStack[sid].back(); 303 DPRINTF(Annotate, "Linking %d back to %d\n", smi, lnMap[smi]); 383 int smi = smStack[sid].back(); 412 // return back to symbol table based states 414 int smi = smStack[sid].back(); [all...] |
/gem5/src/mem/ruby/structures/ |
H A D | WireBuffer.cc | 121 m_message_queue.back() = node;
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/gem5/src/dev/arm/ |
H A D | flash_device.cc | 262 planeEventQueue[count].back().time; 269 schedule(planeEvent, planeEventQueue[count].back().time); 270 else if (planeEventQueue[count].back().time < planeEvent.when()) 272 planeEventQueue[plane_address].back().time, true); 279 planeEventQueue[plane_address].back().function = event;
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