Searched refs:MemSidePort (Results 1 - 10 of 10) sorted by relevance
/gem5/src/learning_gem5/part2/ |
H A D | simple_memobj.hh | 135 class MemSidePort : public MasterPort class in class:SimpleMemobj 148 MemSidePort(const std::string& name, SimpleMemobj *owner) : function in class:SimpleMemobj::MemSidePort 227 MemSidePort memPort;
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H A D | simple_cache.hh | 142 class MemSidePort : public MasterPort class in class:SimpleCache 155 MemSidePort(const std::string& name, SimpleCache *owner) : function in class:SimpleCache::MemSidePort 278 MemSidePort memPort;
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H A D | simple_memobj.cc | 126 SimpleMemobj::MemSidePort::sendPacket(PacketPtr pkt) 139 SimpleMemobj::MemSidePort::recvTimingResp(PacketPtr pkt) 146 SimpleMemobj::MemSidePort::recvReqRetry() 160 SimpleMemobj::MemSidePort::recvRangeChange()
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H A D | simple_cache.cc | 152 SimpleCache::MemSidePort::sendPacket(PacketPtr pkt) 165 SimpleCache::MemSidePort::recvTimingResp(PacketPtr pkt) 172 SimpleCache::MemSidePort::recvReqRetry() 186 SimpleCache::MemSidePort::recvRangeChange()
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/gem5/src/gpu-compute/ |
H A D | tlb_coalescer.hh | 182 class MemSidePort : public MasterPort class in class:TLBCoalescer 185 MemSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer, function in class:TLBCoalescer::MemSidePort 212 std::vector<MemSidePort*> memSidePort;
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H A D | gpu_tlb.hh | 280 * MemSidePort is the TLB Port closer to the memory side 286 class MemSidePort : public MasterPort class in class:X86ISA::GpuTLB 289 MemSidePort(const std::string &_name, GpuTLB * gpu_TLB, function in class:X86ISA::GpuTLB::MemSidePort 309 std::vector<MemSidePort*> memSidePort;
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H A D | tlb_coalescer.cc | 65 memSidePort.push_back(new MemSidePort(csprintf("%s-port%d", name(), i), 220 // MemSidePort::recvReqRetry 371 TLBCoalescer::MemSidePort::recvTimingResp(PacketPtr pkt) 380 TLBCoalescer::MemSidePort::recvReqRetry() 389 TLBCoalescer::MemSidePort::recvFunctional(PacketPtr pkt)
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H A D | gpu_tlb.cc | 122 memSidePort.push_back(new MemSidePort(csprintf("%s-port%d", 1234 // IssueProbeEvent caused by TLBCoalescer::MemSidePort::recvReqRetry 1610 * MemSidePort receives the packet back. 1615 GpuTLB::MemSidePort::recvTimingResp(PacketPtr pkt) 1620 DPRINTF(GPUTLB, "MemSidePort recvTiming for virt_page_addr %#x\n", 1634 GpuTLB::MemSidePort::recvReqRetry()
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/gem5/src/mem/cache/ |
H A D | base.hh | 161 * cache implementation and is used by the MemSidePort. 212 class MemSidePort : public CacheMasterPort class in class:BaseCache 236 MemSidePort(const std::string &_name, BaseCache *_cache, 313 MemSidePort memSidePort;
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H A D | base.cc | 82 memSidePort(p->name + ".mem_side", this, "MemSidePort"), 2542 // MemSidePort 2546 BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt) 2554 BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 2564 BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 2573 BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 2620 BaseCache::MemSidePort::MemSidePort(const std::string &_name,
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