Searched refs:MISCREG_TTBR1 (Results 1 - 7 of 7) sorted by relevance

/gem5/src/arch/arm/
H A Dutility.cc562 case MISCREG_TTBR1:
674 case MISCREG_TTBR1:
H A Dmiscregs.hh192 MISCREG_TTBR1, enumerator in enum:ArmISA::MiscRegIndex
H A Dtable_walker.cc508 MISCREG_TTBR1, currState->tc, !currState->isSecure));
647 MISCREG_TTBR1, currState->tc, !currState->isSecure));
H A Dmiscregs.cc274 return MISCREG_TTBR1;
938 return MISCREG_TTBR1;
3238 InitReg(MISCREG_TTBR1)
H A Dtlb.cc1376 snsBankedIndex(ttbcr.a1 ? MISCREG_TTBR1 :
H A Disa.cc1822 case MISCREG_TTBR1:
/gem5/src/arch/arm/kvm/
H A Darm_cpu.cc659 reg = (id == KVM_REG64_TTBR0 ? MISCREG_TTBR0 : MISCREG_TTBR1);
800 id == KVM_REG64_TTBR0 ? MISCREG_TTBR0 : MISCREG_TTBR1,

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