Searched refs:MISCREG_SIDELEG (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | faults.cc | 70 bits(tc->readMiscReg(MISCREG_SIDELEG), _code) != 0) { |
| H A D | registers.hh | 245 MISCREG_SIDELEG, enumerator in enum:RiscvISA::MiscRegIndex 485 {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}}, |
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