Searched refs:MISCREG_SCAUSE (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | faults.cc | 97 cause = MISCREG_SCAUSE; |
| H A D | registers.hh | 250 MISCREG_SCAUSE, enumerator in enum:RiscvISA::MiscRegIndex 491 {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}}, |
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