Searched refs:MISCREG_PRI_S_WR (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc383 info[MISCREG_PRI_S_WR] || info[MISCREG_PRI_NS_WR] ||
/gem5/src/arch/arm/
H A Disa.hh235 info[MISCREG_PRI_S_WR] = v;
H A Dmiscregs.hh969 MISCREG_PRI_S_WR, enumerator in enum:ArmISA::MiscRegInfo
H A Dmiscregs.cc1042 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1187 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :

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