Searched refs:MISCREG_PMEVCNTR0_EL0 (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/
H A Dpmu.cc265 case MISCREG_PMEVCNTR0_EL0...MISCREG_PMEVCNTR5_EL0:
266 setCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0, val);
371 case MISCREG_PMEVCNTR0_EL0...MISCREG_PMEVCNTR5_EL0: {
372 return getCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0) &
H A Dmiscregs.hh632 MISCREG_PMEVCNTR0_EL0, enumerator in enum:ArmISA::MiscRegIndex
H A Disa.cc581 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1617 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
H A Dmiscregs.cc2685 return MISCREG_PMEVCNTR0_EL0;
4413 InitReg(MISCREG_PMEVCNTR0_EL0)
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc594 { "pmevcntr0_el0", MISCREG_PMEVCNTR0_EL0 },

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