Searched refs:MISCREG_ICV_PMR_EL1 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc359 return readMiscReg(MISCREG_ICV_PMR_EL1);
380 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1283 return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1313 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
/gem5/src/arch/arm/
H A Dmiscregs.hh757 MISCREG_ICV_PMR_EL1, enumerator in enum:ArmISA::MiscRegIndex

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