Searched refs:MISCREG_CYCLE (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Disa.cc78 int hpmcounter = misc_reg - MISCREG_CYCLE;
117 case MISCREG_CYCLE:
118 if (hpmCounterEnabled(MISCREG_CYCLE)) {
157 misc_reg - MISCREG_CYCLE, tc->getCpuPtr()->curCycle());
160 warn("HPM counter %d disabled.\n", misc_reg - MISCREG_CYCLE);
182 if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
H A Dregisters.hh146 MISCREG_CYCLE, enumerator in enum:RiscvISA::MiscRegIndex
450 {CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
532 {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}},

Completed in 9 milliseconds