Searched refs:MISCREG_BANKED_CHILD (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/
H A Disa.hh191 info[MISCREG_BANKED_CHILD] = v;
683 // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
684 lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
685 upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
H A Dmiscregs.hh955 MISCREG_BANKED_CHILD, // The entry is one of the child registers that enumerator in enum:ArmISA::MiscRegInfo
H A Dmiscregs.cc1102 if (miscRegInfo[i][MISCREG_BANKED_CHILD])

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