Searched refs:MISCREG_BANKED (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/
H A Disa.hh183 info[MISCREG_BANKED] = v;
644 if (miscRegInfo[reg][MISCREG_BANKED]) {
H A Dmiscregs.hh949 MISCREG_BANKED, // True if the register is banked between the two enumerator in enum:ArmISA::MiscRegInfo
H A Dmiscregs.cc1020 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1056 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1071 if (miscRegInfo[reg][MISCREG_BANKED]) {
1100 if (miscRegInfo[i][MISCREG_BANKED])

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