Searched refs:GEM5 (Results 1 - 1 of 1) sorted by relevance
| /gem5/ext/sst/tests/ |
| H A D | test6_arm_4c.py | 94 GEM5 = sst.Component("system", "gem5.gem5") variable
95 GEM5.addParams({
117 SysBusConn = buildL1("gem5SystemBus", GEM5, "system.external_memory.port")
123 ioCache = buildL1("ioCache", GEM5, "system.iocache.port")
154 buildCPU(GEM5, 0)
155 buildCPU(GEM5, 1)
156 buildCPU(GEM5, 2)
157 buildCPU(GEM5, 3)
203 sst.Link("l2cache_io_link").connect((comp_chiprtr, "port0", "2ns"), (GEM5, "network", buslat))
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