Searched refs:CSR_SIP (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh322 CSR_SIP = 0x144, enumerator in enum:RiscvISA::CSRIndex
493 {CSR_SIP, {"sip", MISCREG_IP}},
727 {CSR_SIP, SI_MASK},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h794 #define CSR_SIP 0x144 macro
1286 DECLARE_CSR(sip, CSR_SIP)

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